Abstract: Techniques are disclosed relating to using an initial version of an object shader to determine a child count and distribute geometry work based on the child count. In some embodiments, graphics shader circuitry is configured to execute shader programs including object shaders and mesh shaders. Vertex control circuitry is configured to, for a given object shader: launch an initial version of the given object shader to determine a number of meshlets to be generated by the given object shader (e.g., where the initial version of the given object shader does not commit side effects to architectural state of the apparatus) and select shader circuitry to execute a complete version of the given object shader based on the determined number of meshlets.

Abstract: Techniques are disclosed relating to object and mesh shaders executed by a graphics processor. In some embodiments, a device includes buffer circuitry and shader circuitry configured to execute graphics programs. Control circuitry may: generate object shader work and mesh shader work for the shader circuitry, receive output information generated by a mesh shader that indicates a number of vertices and primitives to be output by the mesh shader, allocate, based on the output information and after execution of at least a portion of the mesh shader, a region of the buffer circuitry for storage of the vertices to be output by the mesh shader, and store the vertices output by the mesh shader in the allocated region. Disclosed techniques may advantageously provide efficient use of limited buffer resources.

Abstract: Techniques are disclosed relating to object and mesh shaders executed by a graphics processor. In some embodiments, a device includes buffer circuitry, shader circuitry configured to execute graphics programs, including mesh shaders that store output data in the buffer circuitry, and primitive processing circuitry configured to read data from buffer circuitry and process the data, including to cull primitives that are not visible in a graphics frame. Vertex control circuitry may receive: first signaling from the primitive processing circuitry that indicates whether the primitive processing circuitry is waiting for data from the buffer circuitry and second signaling from the shader circuitry that indicates whether the shader circuitry is blocked waiting for allocation in the buffer circuitry. The vertex control circuitry may adjust distribution of mesh shader work to the shader circuitry based on the first signaling and the second signaling.

Abstract: Disclosed techniques relate to parsing and assigning sets of geometry work to distributed hardware slots. In some embodiments, graphics control circuitry implements a plurality of logical slots. Control circuitry may assign a parse version of a set of geometry work to distributed hardware slots of one or more of the graphics processor sub-units that each implement multiple distributed hardware slots. Control circuitry may determine a number of segments for the set of geometry work based on execution of the parse version and assign determined segments to distributed hardware slots of respective graphics processor sub-units for execution. Stitch circuitry may stitch results of the segments processed by the assigned distributed hardware slots.

Abstract: Techniques are disclosed relating to processing a control stream such as a compute control stream. In some embodiments, the control stream includes kernels and commands for multiple substreams. In some embodiments, multiple substream processors are each configured to: fetch and parse portions of the control stream corresponding to an assigned substream and, in response to a neighbor barrier command in the assigned substream that identifies another substream, communicate the identified other substream to a barrier clearing circuitry. In some embodiments, the barrier clearing circuitry is configured to determine whether to allow the assigned substream to proceed past the neighbor barrier command based on communication of a most-recently-completed command from a substream processor to which the other substream is assigned (e.g., based on whether the most-recently-completed command meets a command identifier communicated in the neighbor barrier command).

Abstract: Techniques are disclosed relating to processing a control stream such as a compute control stream. In some embodiments, the control stream includes kernels and commands for multiple substreams. In some embodiments, multiple substream processors are each configured to: fetch and parse portions of the control stream corresponding to an assigned substream and, in response to a neighbor barrier command in the assigned substream that identifies another substream, communicate the identified other substream to a barrier clearing circuitry. In some embodiments, the barrier clearing circuitry is configured to determine whether to allow the assigned substream to proceed past the neighbor barrier command based on communication of a most-recently-completed command from a substream processor to which the other substream is assigned (e.g., based on whether the most-recently-completed command meets a command identifier communicated in the neighbor barrier command).