Abstract: A multi-bit, asynchronous e-fuse macro, the macro comprising: the following inputs: an input output enable, a power on reset, a write address, an input write enable, a ground clamp enable, and a write clock; a plurality of e-fuse bits; a supply voltage configured to allow programming at least one of the e-fuse bits; at least one fuse output; and self-timing and control circuitry configured to perform signaling, wherein each of the inputs is in electrical communication with said e-fuse macro.

Abstract: An integrated circuit (IC) implements a radiation tolerance limiting feature (RTLF) to ensure that the IC, as manufactured, will fail one or more applicable radiation tolerance tests, for example by reducing or eliminating a required voltage or blocking a required signal. As a result, the IC can be manufactured by any suitable IC foundry, and exported without restriction. The RTLF can include a leakage component, such as an oxide dielectric capacitor, a radiation-sensitive MOSFET or SCR, or a photocurrent generating component. The RTLF can include redundancy to ensure reliability. A plurality of RTLFs can be included to ensure failure of any desired combination of applicable radiation tolerance tests, such as total radiation dosage, linear energy transfer events, radiation dose rate, and single event upset. The RTLF can be obfuscated within the IC design. The RTLF can include a testing output to ensure its functionality.

Abstract: An integrated circuit (IC) that is otherwise radiation tolerant implements a radiation tolerance limiting feature (RTLF) to ensure that the IC, as manufactured, will fail applicable radiation tolerance tests, thereby allowing it to be manufactured by any suitable IC foundry. Embodiments further include a programmable radiation tolerance feature (PRT) that can be actuated at an authorized actuation site after IC manufacture to override the RTLF, thereby rendering the IC radiation tolerant. The PRT and/or RTLF can include redundancy to ensure reliability. The PRT and/or RTLF can be obfuscated, encrypted, and/or password protected. Actuating the PRT can include applying a programming signal to the IC and/or uploading code to a programmable element after IC manufacture. A plurality of RTLFs can be included to ensure failure of any desired combination of applicable radiation tolerance tests, such as total radiation dosage, linear energy transfer events, radiation dose rate, and single event upset.

Abstract: A method for radiation hardening synchronous Dynamic Random Access Memory (DRAM), where Error Detection And Correction (EDAC) is implemented on-chip. Each bank includes a plurality of interleaved single chip Static Random Access Memory (SRAM) cells with bit registers configured to interface with the interleaved SRAM cells. A first column multiplexer (MUX) configured to select which bit register is accessed. A second column multiplexer is configured to select an accessed byte with the WRITE burst or a READ burst from the selected bit registers of the first column multiplexer. EDAC logic is configured to check Error Correction Code (ECC) during a READ burst and generate ECC during an WRITE burst for SRAM writeback during a PRECHARGE command.

Abstract: A level shifting circuit, the circuit comprising a VL input; an I/O VL; a VCC input; an I/O VCC; a first pull-up resistor disposed between the VL input and I/O VL; a second pull-up resistor disposed between the VCC input and I/O VCC; a first pull-up assist circuit comprising a first pull-up assist p-channel MOSFET having a source/body, drain, and gate, the source/body and drain being connected to VL and I/O VL; a second pull-up assist circuit comprising a second pull-up assist p-channel MOSFET having a source/body, drain, and gate, the source/body and drain being connected to VCC and I/O VCC, respectively; a pass-gate n-channel MOSFET in operative communication with I/O VL, I/O VCC, and VL, the pass-gate being configured to reduce the voltage level of a signal driven from I/O VCC to the voltage level of I/O VL; and a one-shot circuit configured to detect a I/O VL or I/O VCC transition from a low state to a high state, to produce a pulse in response thereto, and to communicate that pulse to the gates of the fi

Abstract: A disclosed apparatus and method reduce the likelihood of multiple bit single event upset (SEU) errors in space-deployed memory devices and memory macros. For each memory, a bit selection layer effectively increases the mux of the memory bit table, thereby reducing the word size while increasing the word capacity, without changing the total memory capacity. As a result, the separation between the physical bit storage locations for each word is increased, thereby reducing the likelihood of multiple bit SEU errors. A buffer can be implemented if the memory lacks individual bit write control. The memory can be implemented in a core integrated circuit (IC) of an multi-chip module (MCM) hybrid integrated circuit (HIC), and the bit selection layer and/or buffer can be implemented in a chiplet or chiplets of the MCM-HIC.

Abstract: A disclosed apparatus and method reduce the likelihood of multiple bit single event upset (SEU) errors in space-deployed memory devices and memory macros, without requiring novel, specialized memory designs and without significant added cost or performance loss. For each memory, a bit selection layer effectively increases the mux of the memory bit table, thereby reducing the word size while increasing the word capacity, without changing the total memory capacity. As a result, the separation between the physical bit storage locations for each word is increased, thereby reducing the likelihood of multiple bit SEU errors. A buffer can be implemented if the memory lacks individual bit write control. The memory can be implemented in a core IC of an MCM-HIC, and the bit selection layer and/or buffer can be implemented in a chiplet or chiplets of the MCM-HIC.

Abstract: A multi-chip module hybrid integrated circuit (MCM-HIC) provides cold spare support to an apparatus comprising a plurality of ICs and/or other circuits that are not cold spare compliant. At least one core IC and at least one cold spare chiplet are installed on an interconnecting substrate having a plurality of power zones to which power can be applied and withdrawn as needed. When powered, the cold spare chiplets serve as mediators and interfaces between the non cold spare compliant circuits. When the cold spare chiplets are at least partly unpowered, they protect all interconnected circuits, and ensure that interconnected circuits that remain powered are not hindered by unpowered interconnected circuits. Cold spare chiplets can extend across boundaries between power zones. External circuits can be exclusively interfaced to a subset of the power zones. Separate power circuits within a power zone can be sequenced during application and withdrawal of power.

Abstract: A multi-chip module hybrid integrated circuit (MCM-HIC) provides cold spare support to an apparatus comprising a plurality of ICs and/or other circuits that are not cold spare compliant. At least one core IC and at least one cold spare chiplet are installed on an interconnecting substrate having a plurality of power zones to which power can be applied and withdrawn as needed. When powered, the cold spare chiplets serve as mediators and interfaces between the non cold spare compliant circuits. When the cold spare chiplets are at least partly unpowered, they protect all interconnected circuits, and ensure that interconnected circuits that remain powered are not hindered by unpowered interconnected circuits. Cold spare chiplets can extend across boundaries between power zones. External circuits can be exclusively interfaced to a subset of the power zones. Separate power circuits within a power zone can be sequenced during application and withdrawal of power.

Abstract: A scannable-latch random access memory (SLRAM) is disclosed. The SLRAM includes two rows of memory cells. The SLRAM includes a functional data input, a scan data input, a first and second functional data outputs, a scan data output, and a scan enable. The functional data input is connected to a first memory cell in a first and second rows of memory cells. The scan data input is connected to the first memory cell in the first or second row of memory cells. The first and second functional data outputs are connected to a last memory cell in the first and second row of memory cells, respectively. The scan data output is connected to the last memory cell in the first or second row of memory cells. The scan enable allows data to be output from the scan data output or the first and second functional data outputs.

Abstract: An MCM-HIC device flexibly adds enhanced features to a VLSI “core” IC that are not directly supported by the core IC, such as unsupported communication protocols and/or support of cold spare operation. The core IC is mounted on an interconnecting substrate together with at least one “chiplet” that provides the required feature(s). The chiplet can be programmable. The chiplet can straddle a boundary of an interposer region of the substrate that provides higher density interconnections at lower currents. The disclosed method can include selecting a core IC and at least one active, passive, or “mixed” chiplet, configuring a substrate, and installing the core IC and chiplet(s) on the substrate. In embodiments, the core IC and/or chiplet(s) can be modified before assembly to obtain the desired result. Cost can be reduced by pre-designing and, in embodiments, pre-manufacturing the chiplets and modified core ICs in cost-effective quantities.

Abstract: A system for limiting or diminishing current to unpowered Serializer/Deserializer (SerDes) circuitry is provided. The system comprises receiver input termination circuitry and a cold spare circuitry. The receiver input circuitry comprises a termination resistor and an N-type metal oxide silicon field effect transistor (MOSFET). The cold spare circuitry comprises a first MOSFET and a second MOSFET. When the system is powered on, an input current flows to the receiver input termination circuit to be discharged by the N-type MOSFET which is electrically connected to a ground. When the system is powered off, the input current flows to the cold spare circuitry to discharge the input current. Discharging electrons between the first MOSFET and the second MOSFET depends on the polarity of an accumulated voltage.

Abstract: A scannable-latch random access memory (SLRAM) is disclosed. The SLRAM includes two rows of memory cells. The SLRAM includes a functional data input, a scan data input, a first and second functional data outputs, a scan data output, and a scan enable. The functional data input is connected to a first memory cell in a first and second rows of memory cells. The scan data input is connected to the first memory cell in the first or second row of memory cells. The first and second functional data outputs are connected to a last memory cell in the first and second row of memory cells, respectively. The scan data output is connected to the last memory cell in the first or second row of memory cells. The scan enable allows data to be output from the scan data output or the first and second functional data outputs.

Abstract: An MCM-HIC device flexibly adds enhanced features to a VLSI “core” IC that are not directly supported by the core IC, such as unsupported communication protocols and/or support of cold spare operation. The core IC is mounted on an interconnecting substrate together with at least one “chiplet” that provides the required feature(s). The chiplet can be programmable. The chiplet can straddle a boundary of an interposer region of the substrate that provides higher density interconnections at lower currents. The disclosed method can include selecting a core IC and at least one active, passive, or “mixed” chiplet, configuring a substrate, and installing the core IC and chiplet(s) on the substrate. In embodiments, the core IC and/or chiplet(s) can be modified before assembly to obtain the desired result. Cost can be reduced by pre-designing and, in embodiments, pre-manufacturing the chiplets and modified core ICs in cost-effective quantities.

Abstract: A radiation-hardened electronic system is disclosed. The radiation-hardened electronic system includes a reconfigurable analog circuit block, a digital configuration logic circuit block, and a radiation-hardened isolation latch circuit connecting between the reconfigurable analog circuit block and the digital configuration logic circuit block. The reconfigurable analog circuit block includes multiple analog inputs and outputs. The digital configuration logic circuit block includes multiple digital inputs and outputs for controlling various functionalities of the reconfigurable analog circuit block via a set of configuration data. The radiation-hardened isolation latch circuit prevents the configuration data from entering the reconfigurable analog circuit block when the configuration data has been corrupted by a SEU.

Abstract: A system for limiting or diminishing current to unpowered Serializer/Deserializer (SerDes) circuitry is provided. The system comprises receiver input termination circuitry and a cold spare circuitry. The receiver input circuitry comprises a termination resistor and an N-type metal oxide silicon field effect transistor (MOSFET). The cold spare circuitry comprises a first MOSFET and a second MOSFET. When the system is powered on, an input current flows to the receiver input termination circuit to be discharged by the N-type MOSFET which is electrically connected to a ground. When the system is powered off, the input current flows to the cold spare circuitry to discharge the input current. Discharging electrons between the first MOSFET and the second MOSFET depends on the polarity of an accumulated voltage.

Abstract: An off chip driver circuit includes a bias circuit and a driver sub-cell circuit. The bias circuit and off chip driver sub-cell circuit are in electrical communication with each other. The bias circuit includes two serially aligned diodes which are in an off-state when the driver sub-cell is in a functional mode and which are in an on-state when the driver sub-cell is in a cold spare mode. The arrangement of the diodes enables the off chip driver circuit to handle similar voltage signals in both the functional mode and the cold spare mode.

Abstract: A method for fabricating a metal-insulator-metal capacitor (MIMCap) is disclosed. A first metal layer is provided on top of an oxide layer. A nitride layer is then deposited on the first metal layer. The nitride layer and the first metal layer are etched to form a MIMCap metal layer. The gaps among the MIMCap metal layer are filled with a plasma oxide, and the excess plasma oxide is polished using the nitride layer a polish stop. After removing the nitride layer, a dielectric layer and a second metal layer are deposited on the MIMCap metal layer. Finally, the dielectric layer and the second metal layer are etched to form a set of MIMCap structures.

Abstract: A method for fabricating a metal-insulator-metal capacitor (MIMCap) is disclosed. A first metal layer is provided on top of an oxide layer. A nitride layer is then deposited on the first metal layer. The nitride layer and the first metal layer are etched to form a MIMCap metal layer. The gaps among the MIMCap metal layer are filled with a plasma oxide, and the excess plasma oxide is polished using the nitride layer a polish stop. After removing the nitride layer, a dielectric layer and a second metal layer are deposited on the MIMCap metal layer. Finally, the dielectric layer and the second metal layer are etched to form a set of MIMCap structures.

Abstract: A single event upset (SEU) hardened memory cell to be utilized in static random access memories is disclosed. The SEU hardened memory cell includes a first transistor, a second transistor and a first resistor connected between a source of the first transistor and a drain of the second transistor. The SEU hardened memory cell also includes a third transistor, a fourth transistor and a second resistor connected between a source of the third transistor and a drain of the fourth transistor. The first resistor is also connected between a gate of the third transistor and the drain of the second transistor. The second resistor is also connected between a gate of the first transistor and the drain of the fourth transistor.