Patents by Inventor Jason Higgs

Jason Higgs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and apparatus related to termination regions of a semiconductor device
    Patent number: 10749027
    Abstract: In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth aligned along a vertical axis and have a length aligned along a longitudinal axis orthogonal to the vertical axis. The trench can have a first portion of the length included in a termination region of the semiconductor region and can have a second portion of the length included in an active region of the semiconductor region.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 18, 2020
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Richard Stokes, Jason Higgs, Fred Session
  • METHODS AND APPARATUS RELATED TO TERMINATION REGIONS OF A SEMICONDUCTOR DEVICE
    Publication number: 20190245078
    Abstract: In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth aligned along a vertical axis and have a length aligned along a longitudinal axis orthogonal to the vertical axis. The trench can have a first portion of the length included in a termination region of the semiconductor region and can have a second portion of the length included in an active region of the semiconductor region.
    Type: Application
    Filed: December 28, 2018
    Publication date: August 8, 2019
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Joseph A. Yedinak, Richard Stokes, Jason Higgs, Fred Session
  • Termination region of a semiconductor device
    Patent number: 9496391
    Abstract: In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth aligned along a vertical axis and have a length aligned along a longitudinal axis orthogonal to the vertical axis. The trench can have a first portion of the length included in a termination region of the semiconductor region and can have a second portion of the length included in an active region of the semiconductor region.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: November 15, 2016
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Richard Stokes, Jason Higgs, Fred Session
  • METHODS AND APPARATUS RELATED TO TERMINATION REGIONS OF A SEMICONDUCTOR DEVICE
    Publication number: 20140264569
    Abstract: In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth aligned along a vertical axis and have a length aligned along a longitudinal axis orthogonal to the vertical axis. The trench can have a first portion of the length included in a termination region of the semiconductor region and can have a second portion of the length included in an active region of the semiconductor region.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 18, 2014
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Joseph A. YEDINAK, Dean E. PROBST, Richard STOKES, Suku KIM, Jason HIGGS, Fred SESSION, Hui CHEN, Steven P. SAPP, Jayson PREECE, Mark L. Rinehimer
  • Periphery design for charge balance power devices
    Patent number: 7595542
    Abstract: A charge balance semiconductor power device comprises an active area having strips of p pillars and strips of n pillars arranged in an alternating manner, the strips of p and n pillars extending along a length of the active area. A non-active perimeter region surrounds the active area, and includes at least one p ring surrounding the active area. One end of at last one of the strips of p pillars extending immediately adjacent an edge of the active area terminates at a substantially straight line at which one end of each of the remainder of the strips of p pillars also end. The straight line extends perpendicular to the length of the active area along which the strips of n and p pillars extend.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: September 29, 2009
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Chanho Park, Joseph A. Yedinak, Christopher Boguslaw Kocon, Jason Higgs, Jaegil Lee
  • Periphery design for charge balance power devices
    Publication number: 20070210341
    Abstract: A charge balance semiconductor power device comprises an active area having strips of p pillars and strips of n pillars arranged in an alternating manner, the strips of p and n pillars extending along a length of the active area. A non-active perimeter region surrounds the active area, and includes at least one p ring surrounding the active area. One end of at last one of the strips of p pillars extending immediately adjacent an edge of the active area terminates at a substantially straight line at which one end of each of the remainder of the strips of p pillars also end. The straight line extends perpendicular to the length of the active area along which the strips of n and p pillars extend.
    Type: Application
    Filed: March 13, 2006
    Publication date: September 13, 2007
    Inventors: Chanho Park, Joseph Yedinak, Christopher Kocon, Jason Higgs, Jaegil Lee