Abstract: Techniques for generating preamble sequences for OFDM and OFDMA communication systems based on CAZAC sequences with desired properties of constant amplitudes (CA) and zero autocorrelation (ZAC). Such preamble sequences may be used for synchronization and identification of individual transmitters. For example, the OFDMA symbol is constructed using a CAZAC sequence in the frequency-domain and the resulting time-domain waveform is a near-CAZAC sequence.

Abstract: A karaoke sound system had a mixer that combines the singer's real-time voice signal from a microphone with the pre-recorded background song/music signal from a player, an amplifier that receives the mixed signal from the mixer to provide amplification or gain boosting, a dedicated channel for the vocal signal from the microphone without using a mixing device, one or more speakers to output the mixed and amplified audio signal, and one or more speakers to output the vocal signal from the dedicated channel. The vocal channel allows the vocals to maintain an overall cleaner and vibrant sound, with a “live feeling” positional presence.

Abstract: A synchronous dynamic RAM capable of segmentally precharging each memory bank. In this SDRAM, each memory bank is divided into multiple memory blocks. Each of these memory blocks internally has its own row access circuitry, but performs independent precharging operation. Access to the memory bank can be cooperative externally, and precharge operation can be separately applied to these memory blocks while allowing utilization of row cache that is available on other blocks. The SDRAM further includes a control device for generating a dedicated precharge signal to each memory block according to a precharge signal for each memory bank. Each dedicated precharge signal independently precharges the corresponding memory block regardless of the access operations executed by other memory blocks.

Abstract: A synchronous dynamic RAM capable of segmentally precharging each memory bank. In this SDRAM, each memory bank is divided into multiple memory blocks. Each of these memory blocks internally has its own row access circuitry, but performs independent precharging operation. Access to the memory bank can be cooperative externally, and precharge operation can be separately applied to these memory blocks while allowing utilization of row cache that is available on other blocks. The SDRAM further includes a control device for generating a dedicated precharge signal to each memory block according to a precharge signal for each memory bank. Each dedicated precharge signal independently precharges the corresponding memory block regardless of the access operations executed by other memory blocks.

Abstract: A synchronous dynamic RAM capable of segmentally precharging each memory bank. In this SDRAM, each memory bank is divided into multiple memory blocks. Each of these memory blocks internally has its own row access circuitry, but performs independent precharging operation. Access to the memory bank can be cooperative externally, and precharge operation can be separately applied to these memory blocks while allowing utilization of row cache that is available on other blocks. The SDRAM further includes a control device for generating a dedicated precharge signal to each memory block according to a precharge signal for each memory bank. Each dedicated precharge signal independently precharges the corresponding memory block regardless of the access operations executed by other memory blocks.