Patents by Inventor Jason Hu
Jason Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240429908Abstract: A system includes a comparator having a first input, a second input, and an output. The system also includes a first voltage divider having an input and an output, wherein the input of the first voltage divider is coupled to a first power rail, and the output of the first voltage divider is coupled to the first input of the comparator. The system also includes a second voltage divider having an input and an output, wherein the input of the second voltage divider is coupled to a second power rail, and the output of the second voltage divider is coupled to the second input of the comparator. The system further includes a power multiplexer coupled to the first power rail, the second power rail, and a first circuit, and a control circuit coupled to the output of the comparator and the power multiplexer.Type: ApplicationFiled: June 23, 2023Publication date: December 26, 2024Inventors: Harshat PANT, Hanil LEE, Shih-Hsin Jason HU, Chulmin JUNG, Xiao CHEN, Christol BARNES
-
Patent number: 11880454Abstract: A method to prevent a malicious attack on CPU subsystem (CPUSS) hardware is described. The method includes auto-calibrating tunable delay elements of a dynamic variation monitor (DVM) using an auto-calibration value computed in response to each detected change of a clock frequency (Fclk)/supply voltage (Vdd) of the CPUSS hardware. The method also includes comparing the auto-calibration value with a threshold reference calibration value to determine whether the malicious attack is detected. The method further includes forcing a safe clock frequency (Fclk)/safe supply voltage (Vdd) to the CPUSS hardware when the malicious attack is detected.Type: GrantFiled: May 14, 2020Date of Patent: January 23, 2024Assignee: QUALCOMM IncorporatedInventors: Bharat Kumar Rangarajan, Dipti Ranjan Pal, Keith Alan Bowman, Srinivas Turaga, Ateesh Deepankar De, Shih-Hsin Jason Hu, Chandan Agarwalla
-
Publication number: 20230421156Abstract: An aspect relates to a glitch absorbing buffer (GABUF) including: a delay element configured to delay an input signal by a delay to generate a delayed input signal; and a logic circuit, responsive to the input signal, the delayed input signal, and an output signal, configured to propagate a pulse in the input signal to the output signal if a width of the pulse is greater than the delay, and suppress the propagating of the pulse to the output signal if the width of the pulse is less than the delay.Type: ApplicationFiled: June 24, 2022Publication date: December 28, 2023Inventors: Basma HAJRI, Harshat PANT, Chirag AGRAWAL, Shih-Hsin Jason HU
-
Publication number: 20230285867Abstract: A ride feature is disclosed using conjoined bowl structures formed of multiple bowl structures attached to each other. In a two bowl embodiment, the ride vehicle rides about at least a portion of a periphery of a first bowl structure and then about at least a portion of a periphery of a second bowl structure before exiting the ride feature. The ride vehicle may exit the conjoined bowl structure from either the first bowl structure or the second bowl structure. In alternative embodiments, the conjoined bowl feature may be comprised of more than two conjoined bowls, the bowls may be of different diameter, and/or the bowls may have a constantly decreasing or increasing diameter.Type: ApplicationFiled: November 15, 2022Publication date: September 14, 2023Inventors: Claudio Barrera, Jason Hu, Ben Cornwall-Mott, Ross Flavell, Bruce Bradley
-
Patent number: 11249530Abstract: In certain aspects, a system includes a voltage controller, wherein the voltage controller includes switches coupled between a voltage supply rail and an output of the voltage controller, each of the switches having a control input, and a control circuit coupled to the control inputs of the switches. The system also includes a timing circuit coupled to the control circuit, wherein the timing circuit includes a delay line, and flops, each of the flops having an input and an output, wherein the input of each of the flops is coupled to a respective node on the delay line, and the outputs of the flops are coupled to the control circuit.Type: GrantFiled: November 25, 2020Date of Patent: February 15, 2022Assignee: QUALCOMM INCORPORATEDInventors: Dipti Ranjan Pal, Harshat Pant, Abinash Roy, Shih-Hsin Jason Hu, Keith Alan Bowman
-
Publication number: 20210357502Abstract: A method to prevent a malicious attack on CPU subsystem (CPUSS) hardware is described. The method includes auto-calibrating tunable delay elements of a dynamic variation monitor (DVM) using an auto-calibration value computed in response to each detected change of a clock frequency (Fclk)/supply voltage (Vdd) of the CPUSS hardware. The method also includes comparing the auto-calibration value with a threshold reference calibration value to determine whether the malicious attack is detected. The method further includes forcing a safe clock frequency (Fclk)/safe supply voltage (Vdd) to the CPUSS hardware when the malicious attack is detected.Type: ApplicationFiled: May 14, 2020Publication date: November 18, 2021Inventors: Bharat Kumar RANGARAJAN, Dipti Ranjan PAL, Keith Alan BOWMAN, Srinivas TURAGA, Ateesh Deepankar DE, Shih-Hsin Jason HU, Chandan AGARWALLA
-
Publication number: 20200264229Abstract: Aspects of the present disclosure provide techniques for predicting a failure of an integrated circuit, which may include receiving first aging sensor data during an idle state of the integrated circuit; determining a voltage compensation value based on the first aging sensor data; comparing a new voltage value based on the voltage compensation value to a threshold operating voltage; determining the new operating voltage value exceeds the threshold operating voltage; determining a warning state for the integrated circuit; receiving second aging sensor data during the idle state of the integrated circuit; receiving stored aging sensor data from an aging sensor data repository; comparing the second aging sensor data to the stored aging sensor data; determining that the second aging sensor data is inconsistent with the stored aging sensor data; and determining a danger state for the integrated circuit.Type: ApplicationFiled: February 15, 2019Publication date: August 20, 2020Inventors: Uttkarsh WARDHAN, Madan M. KRISHNAPPA, Shih-Hsin Jason HU, Min CHEN
-
Patent number: 10359833Abstract: A hardware system is disclosed for active-core-based performance boost. In an example aspect, the hardware system includes multiple cores and a power mode manager. Each core can be powered up if active or powered down if inactive. The power mode manager manages a power mode collection including an independent power mode collection and an active-core-dependent power mode collection. The power mode manager includes a software-accessible power mode manager and a hardware-reserved power mode manager. The software-accessible power mode manager provides a power-mode-triggering pathway to enable software to trigger activation of an independent power mode of the independent power mode collection. The hardware-reserved power mode manager excludes the software from being able to trigger activation of a dependent power mode of the active-core-dependent power mode collection and triggers activation of a dependent power mode of the active-core-dependent collection based on a number of active cores of the multiple cores.Type: GrantFiled: June 20, 2016Date of Patent: July 23, 2019Assignee: QUALCOMM IncorporatedInventors: Sarbartha Banerjee, Pawan Chhabra, Navid Toosizadeh, Sreekanth Nallagatla, Shih-Hsin Jason Hu
-
Patent number: 10103714Abstract: Apparatuses and methods to adjust voltage for thermal mitigation are provided. The apparatus includes a circuit, a plurality of switches configured to provide power of a power domain to the circuit, a plurality of thermal sensors disposed at different locations about the circuit and configured to detect temperatures at the different locations, and a control circuit configured to determine that one of the detected temperatures at one of the locations exceeds a temperature threshold, and in response, adjust one or more of the plurality of switches in proximity with the one location to reduce power provided to the circuit. The method includes providing power of a power domain through a plurality of switches, detecting a temperature at a location exceeding a temperature threshold, and adjusting the plurality of switches in proximity with the location to reduce the power provided, in response to the detecting the temperature exceeding the temperature threshold.Type: GrantFiled: March 1, 2016Date of Patent: October 16, 2018Assignee: QUALCOMM IncorporatedInventors: Palkesh Jain, Manoj Mehrotra, Yuancheng Chris Pan, Shih-Hsin Jason Hu
-
Publication number: 20180183417Abstract: In certain aspects, a system comprises a voltage-droop mitigation circuit configured to monitor voltage droop in a supply voltage supplied to a circuit, and to perform voltage-droop mitigation for the circuit if the monitored voltage droop is equal to or greater than a droop threshold. In one aspect, the system also includes a performance monitor configured to track a number of clock cycles over which the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of clock cycles. In another aspect, the system also includes a performance monitor configured to track a number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within the time duration.Type: ApplicationFiled: December 28, 2016Publication date: June 28, 2018Inventors: Lam Ho, Keith Alan Bowman, Navid Toosizadeh, Shih-Hsin Jason Hu, Mohammad Reza Kakoee, Saravana Krishnan Kannan
-
Patent number: 10009016Abstract: In certain aspects, a system comprises a voltage-droop mitigation circuit configured to monitor voltage droop in a supply voltage supplied to a circuit, and to perform voltage-droop mitigation for the circuit if the monitored voltage droop is equal to or greater than a droop threshold. In one aspect, the system also includes a performance monitor configured to track a number of clock cycles over which the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of clock cycles. In another aspect, the system also includes a performance monitor configured to track a number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within the time duration.Type: GrantFiled: December 28, 2016Date of Patent: June 26, 2018Assignee: QUALCOMM IncorporatedInventors: Lam Ho, Keith Alan Bowman, Navid Toosizadeh, Shih-Hsin Jason Hu, Mohammad Reza Kakoee, Saravana Krishnan Kannan
-
Patent number: 9990024Abstract: A method including receiving an indication of a number of active processing units in a computer processor; in response to receiving the indication, determining an appropriate operating voltage margin for the computer processor; reducing an operating frequency of the active processing units in response to receiving the indication; adjusting a power supply to increase or decrease a voltage to the computer processor in accordance with the appropriate operating voltage margin; and increasing the operating frequency of the active processing units in response to an acknowledgment that the power supply has been adjusted.Type: GrantFiled: September 9, 2015Date of Patent: June 5, 2018Assignee: QUALCOMM IncorporatedInventors: Navid Toosizadeh, Mohammad Reza Kakoee, Shih-Hsin Jason Hu, Mohamed Waleed Allam
-
Publication number: 20180004689Abstract: An apparatus includes a memory, a timing circuit configured to emulate a first operation of the memory to activate a second operation of the memory, a sensor configured to emulate a portion of the timing circuit, and a controller configured to adjust an operating parameter of the memory based on the sensor emulating the portion of the timing circuit. A method is presented. The method includes at least operating a timing circuit to emulate a first operation of the memory, activating a second operation of the memory based on the emulating the first operation of the memory, emulating, by a sensor, a portion of the timing circuit. Another apparatus is presented. The apparatus includes at least a memory, a timing circuit, and means for tracking a performance of the memory based on the timing circuit tracking a memory operation.Type: ApplicationFiled: June 29, 2016Publication date: January 4, 2018Inventors: Percy Tehmul MARFATIA, Rajagopal NARAYANAN, Shih-Hsin Jason HU, Nan CHEN
-
Patent number: 9858217Abstract: An apparatus includes a memory, a timing circuit configured to emulate a first operation of the memory to activate a second operation of the memory, a sensor configured to emulate a portion of the timing circuit, and a controller configured to adjust an operating parameter of the memory based on the sensor emulating the portion of the timing circuit. A method is presented. The method includes at least operating a timing circuit to emulate a first operation of the memory, activating a second operation of the memory based on the emulating the first operation of the memory, emulating, by a sensor, a portion of the timing circuit. Another apparatus is presented. The apparatus includes at least a memory, a timing circuit, and means for tracking a performance of the memory based on the timing circuit tracking a memory operation.Type: GrantFiled: June 29, 2016Date of Patent: January 2, 2018Assignee: QUALCOMM IncorporatedInventors: Percy Tehmul Marfatia, Rajagopal Narayanan, Shih-Hsin Jason Hu, Nan Chen
-
Publication number: 20170364140Abstract: A hardware system is disclosed for active-core-based performance boost. In an example aspect, the hardware system includes multiple cores and a power mode manager. Each core can be powered up if active or powered down if inactive. The power mode manager manages a power mode collection including an independent power mode collection and an active-core-dependent power mode collection. The power mode manager includes a software-accessible power mode manager and a hardware-reserved power mode manager. The software-accessible power mode manager provides a power-mode-triggering pathway to enable software to trigger activation of an independent power mode of the independent power mode collection. The hardware-reserved power mode manager excludes the software from being able to trigger activation of a dependent power mode of the active-core-dependent power mode collection and triggers activation of a dependent power mode of the active-core-dependent collection based on a number of active cores of the multiple cores.Type: ApplicationFiled: June 20, 2016Publication date: December 21, 2017Inventors: Sarbartha Banerjee, Pawan Chhabra, Navid Toosizadeh, Sreekanth Nallagatla, Shih-Hsin Jason Hu
-
Publication number: 20170257079Abstract: Apparatuses and methods to adjust voltage for thermal mitigation are provided. The apparatus includes a circuit, a plurality of switches configured to provide power of a power domain to the circuit, a plurality of thermal sensors disposed at different locations about the circuit and configured to detect temperatures at the different locations, and a control circuit configured to determine that one of the detected temperatures at one of the locations exceeds a temperature threshold, and in response, adjust one or more of the plurality of switches in proximity with the one location to reduce power provided to the circuit. The method includes providing power of a power domain through a plurality of switches, detecting a temperature at a location exceeding a temperature threshold, and adjusting the plurality of switches in proximity with the location to reduce the power provided, in response to the detecting the temperature exceeding the temperature threshold.Type: ApplicationFiled: March 1, 2016Publication date: September 7, 2017Inventors: Palkesh JAIN, Manoj MEHROTRA, Yuancheng Chris PAN, Shih-Hsin Jason HU
-
Publication number: 20170247905Abstract: A collapsible shelter is provided and is in the form of a self-locking and inverting canopy that can be moved between a collapsed state to an in-use state by applying an inversion force to a central hub.Type: ApplicationFiled: February 22, 2017Publication date: August 31, 2017Inventors: Anthony Topping, Eric Lam Chi Keung, Adam Tavin, Howard Allen Wilson, IV, Jason Hu, Artem Mishin
-
Patent number: D890350Type: GrantFiled: January 7, 2020Date of Patent: July 14, 2020Assignee: ZeroBrush, Inc.Inventors: Nidhi Pai, Ria Pai, Jason Hu, Akash Pai
-
Patent number: D908223Type: GrantFiled: June 16, 2020Date of Patent: January 19, 2021Assignee: ZeroBrush, Inc.Inventors: Nidhi Pai, Ria Pai, Jason Hu, Akash Pai
-
Patent number: D939091Type: GrantFiled: December 17, 2020Date of Patent: December 21, 2021Assignee: ZEROBRUSH, INC.Inventors: Nidhi Pai, Ria Pai, Jason Hu, Akash Pai