Patents by Inventor Jason Hu

Jason Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250115608
    Abstract: The invention relates to activators of FXR useful in the treatment of autoimmune disorders, liver disease, intestinal disease, kidney disease, cancer, and other diseases in which FXR plays a role, having the Formula (I): wherein L1, A, X1, X2, R1, R2, and R3 are described herein.
    Type: Application
    Filed: December 11, 2024
    Publication date: April 10, 2025
    Applicant: ARDELYX, INC.
    Inventors: Jianhua Chao, Rakesh Jain, Lily Hu, Jason Gustaf Lewis, Helene Baribault, Jeremy Caldwell
  • Patent number: 12271289
    Abstract: A system, e.g., a system on a chip (SoC) includes a first domain including a first processor configured to boot the system; a second domain including a processing subsystem having a second processor; and isolation circuitry between the first domain and the second domain During boot-up of the system, the first processor provides code to the second domain. When the code is executed by the second processor, it configures the processing subsystem as either a safety domain or as a general-purpose processing domain. The safety domain may an external safety domain or an internal safety domain.
    Type: Grant
    Filed: January 3, 2024
    Date of Patent: April 8, 2025
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Venkateswar Kowkutla, Raghavendra Santhanagopal, Chunhua Hu, Anthony Frederick Seely, Nishanth Menon, Rajesh Kumar Vanga, Rejitha Nair, Siva Srinivas Kothamasu, Kazunobu Shin, Jason Peck, John Apostol
  • Publication number: 20250094370
    Abstract: Eyewear including a frame having a first side and a second side, a first temple extending from the first side of the frame, a second temple extending from the second side of the frame, electronic components, a first system on a chip (SoC) adjacent the first side of the frame coupled to a first set of the electronic components, and a second system on a chip adjacent the second side, the second SoC coupled to the first SoC and to a second set of the plurality of electronic components. Processing workloads are balanced between the first SoC and the second SoC by performing a first set of operations with the first SoC and performing a second set of operations with the second SoC.
    Type: Application
    Filed: December 4, 2024
    Publication date: March 20, 2025
    Inventors: Praveen Babu Vadivelu, Jason Heger, Gerald Nilles, Alex Feinman, Dunxu Hu
  • Patent number: 12216519
    Abstract: Methods and systems are disclosed for detecting whether a wearable device is being worn by a user. The system transmits a radio signal from a first communication device of a wearable device to a second communication device of the wearable device and measures a signal strength associated with the radio signal received by the second communication device. The system compares the signal strength to a threshold value and generates an indication of a wear status associated with the wearable device based on comparing the signal strength to the threshold value.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: February 4, 2025
    Assignee: Snap Inc.
    Inventors: Jason Heger, Dunxu Hu, Eric Nachtigall, Gerald Nilles, Ugur Olgun, Praveen Babu Vadivelu
  • Publication number: 20250034328
    Abstract: A copolyester is provided comprising: a. at least one terephthalate acid residue; b. about 85 to about 96 mole % of ethylene glycol residues; c. about 4 to about 15 mole % of a combination of 1,4-cyclohexanedimethanol residues (CHDM) and diethylene glycol (DEG) residues; and d. a germanium catalyst present in the copolyester at a concentration of about 5 to about 500 ppm based on elemental germanium; wherein the terephthalate monomer is based on the substantially equal diacid equivalents of 100 mole % to diol equivalence of 100 mole % for a total of 200 mole %.
    Type: Application
    Filed: August 25, 2022
    Publication date: January 30, 2025
    Applicant: Eastman Chemical Company
    Inventors: Joshua Seth Cannon, Coralie McKenna Fleenor, Scott Ellery George, Huamin Hu, Mark Allan Treece, Carolin Adleheid Vogel, Matthew Robert Kita, Jason Scott Woods, Jonathan Michael Horton
  • Patent number: 12209088
    Abstract: The invention relates to activators of FXR useful in the treatment of autoimmune disorders, liver disease, intestinal disease, kidney disease, cancer, and other diseases in which FXR plays a role, having the Formula (I): wherein L1, A, X1, X2, R1, R2, and R3 are described herein.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: January 28, 2025
    Assignee: ARDELYX, INC.
    Inventors: Jianhua Chao, Rakesh Jain, Lily Hu, Jason Gustaf Lewis, Helene Baribault, Jeremy Caldwell
  • Publication number: 20240429908
    Abstract: A system includes a comparator having a first input, a second input, and an output. The system also includes a first voltage divider having an input and an output, wherein the input of the first voltage divider is coupled to a first power rail, and the output of the first voltage divider is coupled to the first input of the comparator. The system also includes a second voltage divider having an input and an output, wherein the input of the second voltage divider is coupled to a second power rail, and the output of the second voltage divider is coupled to the second input of the comparator. The system further includes a power multiplexer coupled to the first power rail, the second power rail, and a first circuit, and a control circuit coupled to the output of the comparator and the power multiplexer.
    Type: Application
    Filed: June 23, 2023
    Publication date: December 26, 2024
    Inventors: Harshat PANT, Hanil LEE, Shih-Hsin Jason HU, Chulmin JUNG, Xiao CHEN, Christol BARNES
  • Patent number: 11880454
    Abstract: A method to prevent a malicious attack on CPU subsystem (CPUSS) hardware is described. The method includes auto-calibrating tunable delay elements of a dynamic variation monitor (DVM) using an auto-calibration value computed in response to each detected change of a clock frequency (Fclk)/supply voltage (Vdd) of the CPUSS hardware. The method also includes comparing the auto-calibration value with a threshold reference calibration value to determine whether the malicious attack is detected. The method further includes forcing a safe clock frequency (Fclk)/safe supply voltage (Vdd) to the CPUSS hardware when the malicious attack is detected.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: January 23, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Bharat Kumar Rangarajan, Dipti Ranjan Pal, Keith Alan Bowman, Srinivas Turaga, Ateesh Deepankar De, Shih-Hsin Jason Hu, Chandan Agarwalla
  • Publication number: 20230421156
    Abstract: An aspect relates to a glitch absorbing buffer (GABUF) including: a delay element configured to delay an input signal by a delay to generate a delayed input signal; and a logic circuit, responsive to the input signal, the delayed input signal, and an output signal, configured to propagate a pulse in the input signal to the output signal if a width of the pulse is greater than the delay, and suppress the propagating of the pulse to the output signal if the width of the pulse is less than the delay.
    Type: Application
    Filed: June 24, 2022
    Publication date: December 28, 2023
    Inventors: Basma HAJRI, Harshat PANT, Chirag AGRAWAL, Shih-Hsin Jason HU
  • Publication number: 20230285867
    Abstract: A ride feature is disclosed using conjoined bowl structures formed of multiple bowl structures attached to each other. In a two bowl embodiment, the ride vehicle rides about at least a portion of a periphery of a first bowl structure and then about at least a portion of a periphery of a second bowl structure before exiting the ride feature. The ride vehicle may exit the conjoined bowl structure from either the first bowl structure or the second bowl structure. In alternative embodiments, the conjoined bowl feature may be comprised of more than two conjoined bowls, the bowls may be of different diameter, and/or the bowls may have a constantly decreasing or increasing diameter.
    Type: Application
    Filed: November 15, 2022
    Publication date: September 14, 2023
    Inventors: Claudio Barrera, Jason Hu, Ben Cornwall-Mott, Ross Flavell, Bruce Bradley
  • Patent number: 11249530
    Abstract: In certain aspects, a system includes a voltage controller, wherein the voltage controller includes switches coupled between a voltage supply rail and an output of the voltage controller, each of the switches having a control input, and a control circuit coupled to the control inputs of the switches. The system also includes a timing circuit coupled to the control circuit, wherein the timing circuit includes a delay line, and flops, each of the flops having an input and an output, wherein the input of each of the flops is coupled to a respective node on the delay line, and the outputs of the flops are coupled to the control circuit.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: February 15, 2022
    Assignee: QUALCOMM INCORPORATED
    Inventors: Dipti Ranjan Pal, Harshat Pant, Abinash Roy, Shih-Hsin Jason Hu, Keith Alan Bowman
  • Publication number: 20210357502
    Abstract: A method to prevent a malicious attack on CPU subsystem (CPUSS) hardware is described. The method includes auto-calibrating tunable delay elements of a dynamic variation monitor (DVM) using an auto-calibration value computed in response to each detected change of a clock frequency (Fclk)/supply voltage (Vdd) of the CPUSS hardware. The method also includes comparing the auto-calibration value with a threshold reference calibration value to determine whether the malicious attack is detected. The method further includes forcing a safe clock frequency (Fclk)/safe supply voltage (Vdd) to the CPUSS hardware when the malicious attack is detected.
    Type: Application
    Filed: May 14, 2020
    Publication date: November 18, 2021
    Inventors: Bharat Kumar RANGARAJAN, Dipti Ranjan PAL, Keith Alan BOWMAN, Srinivas TURAGA, Ateesh Deepankar DE, Shih-Hsin Jason HU, Chandan AGARWALLA
  • Publication number: 20200264229
    Abstract: Aspects of the present disclosure provide techniques for predicting a failure of an integrated circuit, which may include receiving first aging sensor data during an idle state of the integrated circuit; determining a voltage compensation value based on the first aging sensor data; comparing a new voltage value based on the voltage compensation value to a threshold operating voltage; determining the new operating voltage value exceeds the threshold operating voltage; determining a warning state for the integrated circuit; receiving second aging sensor data during the idle state of the integrated circuit; receiving stored aging sensor data from an aging sensor data repository; comparing the second aging sensor data to the stored aging sensor data; determining that the second aging sensor data is inconsistent with the stored aging sensor data; and determining a danger state for the integrated circuit.
    Type: Application
    Filed: February 15, 2019
    Publication date: August 20, 2020
    Inventors: Uttkarsh WARDHAN, Madan M. KRISHNAPPA, Shih-Hsin Jason HU, Min CHEN
  • Patent number: 10359833
    Abstract: A hardware system is disclosed for active-core-based performance boost. In an example aspect, the hardware system includes multiple cores and a power mode manager. Each core can be powered up if active or powered down if inactive. The power mode manager manages a power mode collection including an independent power mode collection and an active-core-dependent power mode collection. The power mode manager includes a software-accessible power mode manager and a hardware-reserved power mode manager. The software-accessible power mode manager provides a power-mode-triggering pathway to enable software to trigger activation of an independent power mode of the independent power mode collection. The hardware-reserved power mode manager excludes the software from being able to trigger activation of a dependent power mode of the active-core-dependent power mode collection and triggers activation of a dependent power mode of the active-core-dependent collection based on a number of active cores of the multiple cores.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: July 23, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Sarbartha Banerjee, Pawan Chhabra, Navid Toosizadeh, Sreekanth Nallagatla, Shih-Hsin Jason Hu
  • Patent number: 10103714
    Abstract: Apparatuses and methods to adjust voltage for thermal mitigation are provided. The apparatus includes a circuit, a plurality of switches configured to provide power of a power domain to the circuit, a plurality of thermal sensors disposed at different locations about the circuit and configured to detect temperatures at the different locations, and a control circuit configured to determine that one of the detected temperatures at one of the locations exceeds a temperature threshold, and in response, adjust one or more of the plurality of switches in proximity with the one location to reduce power provided to the circuit. The method includes providing power of a power domain through a plurality of switches, detecting a temperature at a location exceeding a temperature threshold, and adjusting the plurality of switches in proximity with the location to reduce the power provided, in response to the detecting the temperature exceeding the temperature threshold.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: October 16, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Palkesh Jain, Manoj Mehrotra, Yuancheng Chris Pan, Shih-Hsin Jason Hu
  • Publication number: 20180183417
    Abstract: In certain aspects, a system comprises a voltage-droop mitigation circuit configured to monitor voltage droop in a supply voltage supplied to a circuit, and to perform voltage-droop mitigation for the circuit if the monitored voltage droop is equal to or greater than a droop threshold. In one aspect, the system also includes a performance monitor configured to track a number of clock cycles over which the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of clock cycles. In another aspect, the system also includes a performance monitor configured to track a number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within the time duration.
    Type: Application
    Filed: December 28, 2016
    Publication date: June 28, 2018
    Inventors: Lam Ho, Keith Alan Bowman, Navid Toosizadeh, Shih-Hsin Jason Hu, Mohammad Reza Kakoee, Saravana Krishnan Kannan
  • Patent number: 10009016
    Abstract: In certain aspects, a system comprises a voltage-droop mitigation circuit configured to monitor voltage droop in a supply voltage supplied to a circuit, and to perform voltage-droop mitigation for the circuit if the monitored voltage droop is equal to or greater than a droop threshold. In one aspect, the system also includes a performance monitor configured to track a number of clock cycles over which the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of clock cycles. In another aspect, the system also includes a performance monitor configured to track a number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within a time duration, and to adjust the droop threshold based on the number of times that the voltage-droop mitigation circuit performs the voltage-droop mitigation within the time duration.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: June 26, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Lam Ho, Keith Alan Bowman, Navid Toosizadeh, Shih-Hsin Jason Hu, Mohammad Reza Kakoee, Saravana Krishnan Kannan
  • Patent number: D890350
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: July 14, 2020
    Assignee: ZeroBrush, Inc.
    Inventors: Nidhi Pai, Ria Pai, Jason Hu, Akash Pai
  • Patent number: D908223
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: January 19, 2021
    Assignee: ZeroBrush, Inc.
    Inventors: Nidhi Pai, Ria Pai, Jason Hu, Akash Pai
  • Patent number: D939091
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: December 21, 2021
    Assignee: ZEROBRUSH, INC.
    Inventors: Nidhi Pai, Ria Pai, Jason Hu, Akash Pai