Abstract: Digital isolators operable in multiple power modes are described. The digital isolators include a low power mode, in which some circuitry of the isolator operates in a lower power state than in other mode(s) of operation or may be deactivated, and in which data communication across the isolator is not permitted. The isolator may wake from the low power mode in response to a detected event or may periodically wake. Circuitry on one side of the isolator may dictate when and how the isolator wakes from a lower power mode.

Abstract: Methods and apparatus are disclosed for communicating multiple logic states across a digital isolator. The digital isolator is a universal serial bus (USB) isolator in some embodiments. The digital isolator includes one or more single-bit data channels. Three or more logic states of information are transmitted across the single-bit data channel(s). The logic states are distinguished by a pulse sequence, and in particular a number of edges of the pulse sequence and a final value or final edge of the pulse sequence.

Abstract: Methods and apparatus are disclosed for communicating multiple logic states across a digital isolator. The digital isolator is a universal serial bus (USB) isolator in some embodiments. The digital isolator includes one or more single-bit data channels. Three or more logic states of information are transmitted across the single-bit data channel(s). The logic states are distinguished by a pulse sequence, and in particular a number of edges of the pulse sequence and a final value or final edge of the pulse sequence.

Abstract: A first circuit board includes a master device and slave devices communicating with each other via a local first I2C bus. To allow I2C networks to communicate with each other over long distances, such as up to 1200 meters, a first interface device converts the I2C data signals to encoded differential data over a twisted wire pair. A second interface device on a remote circuit board converts the differential data to data and clock signals on its local second I2C bus coupled to other slave devices on the same board. This is equivalent to the two boards sharing the same I2C bus. The interface devices pull down the serial clock line (SCL) in their local I2C bus while waiting for data, such as an acknowledge bit. The master device generates the clock signal for its local I2C bus, and the remote interface device generates the clock signal for its local I2C bus.

Abstract: A first circuit board includes a master device and slave devices communicating with each other via a local first I2C bus. To allow I2C networks to communicate with each other over long distances, such as up to 1200 meters, a first interface device converts the I2C data signals to encoded differential data over a twisted wire pair. A second interface device on a remote circuit board converts the differential data to data and clock signals on its local second I2C bus coupled to other slave devices on the same board. This is equivalent to the two boards sharing the same I2C bus. The interface devices pull down the serial clock line (SCL) in their local I2C bus while waiting for data, such as an acknowledge bit. The master device generates the clock signal for its local I2C bus, and the remote interface device generates the clock signal for its local I2C bus.

Abstract: Some embodiments includes a digital control system having a microcontroller to handle a first command associated with a first operation of a memory device, and circuitry coupled to the microcontroller to handle a second command associated with a second operation of the memory device without involving the microcontroller in the second operation.