Abstract: Techniques relating to synthesizing masks for use in manufacturing a semiconductor device are disclosed. These techniques include providing, by a processor, a design pattern for a semiconductor device as input to a trained machine learning (ML) model. The techniques further include performing, using the ML Model, a plurality of dilated convolutions relating to the design pattern, and inferring, using the ML model, one or more masks for use in manufacturing the semiconductor device, based on the plurality of dilated convolutions.

Abstract: Techniques relating to synthesizing masks for use in manufacturing a semiconductor device are disclosed. A plurality of training masks, for a machine learning (ML) model, are generated by synthesizing one or more polygons, relating to a design pattern for the semiconductor device, using Inverse Lithography Technology (ILT) (106). The ML model is trained using both the plurality of training masks generated using ILT, and the design pattern for the semiconductor device, as inputs (108). The trained ML model is configured to synthesize one or more masks, for use in manufacturing the semiconductor device, based on the design pattern (110).

Abstract: Techniques relating to synthesizing masks for use in manufacturing a semiconductor device are disclosed. A plurality of training masks, for a machine learning (ML) model, are generated by synthesizing one or more polygons, relating to a design pattern for the semiconductor device, using Inverse Lithography Technology (ILT) (106). The ML model is trained using both the plurality of training masks generated using ILT, and the design pattern for the semiconductor device, as inputs (108). The trained ML model is configured to synthesize one or more masks, for use in manufacturing the semiconductor device, based on the design pattern (110).