Abstract: Transistor structures with gate material self-aligned to underlying channel material. A channel mask material employed for patterning channel material is retained during selective formation of a second mask material upon exposed surfaces of gate material. The channel mask material is then thinned to expose a sidewall of adjacent gate material. The exposed gate material sidewall is laterally recessed to expand an opening beyond an edge of underlying channel material. A third mask material may be formed in the expanded opening to protect an underlying portion of gate material during a gate etch that forms a trench bifurcating the underlying portion of gate material from an adjacent portion of gate material. The underlying portion of gate material extends laterally beyond the channel material by an amount that is substantially symmetrical about a centerline of the channel material and this amount has a height well controlled relative to the channel material.

Abstract: A method of manufacturing a metal gate structure includes providing a substrate (110) having formed thereon a gate dielectric (120), a work function metal (130) adjacent to the gate dielectric, and a gate metal (140) adjacent to the work function metal; selectively forming a sacrificial capping layer (310) centered over the gate metal; forming an electrically insulating layer (161) over the sacrificial capping layer such that the electrically insulating layer at least partially surrounds the sacrificial capping layer; selectively removing the sacrificial capping layer in order to form a trench (410) aligned to the gate metal in the electrically insulating layer; and filling the trench with an electrically insulating material in order to form an electrically insulating cap (150) centered on the gate metal.

Abstract: Interconnect structures having improved adhesion and electromigration performance and methods to fabricate thereof are described. A tensile capping layer is formed on a first conductive layer on a substrate. A compressive capping layer is formed on the tensile capping layer. Next, an interlayer dielectric layer is formed on the compressive capping layer. Further, a first opening is formed in the ILD layer using a first chemistry. A second opening is formed in the tensile capping layer and the compressive capping layer using a second chemistry. Next, a second conductive layer is formed in the first opening and the second opening.

Abstract: A method of manufacturing a metal gate structure includes providing a substrate (110) having formed thereon a gate dielectric (120), a work function metal (130) adjacent to the gate dielectric, and a gate metal (140) adjacent to the work function metal; selectively forming a sacrificial capping layer (310) centered over the gate metal; forming an electrically insulating layer (161) over the sacrificial capping layer such that the electrically insulating layer at least partially surrounds the sacrificial capping layer; selectively removing the sacrificial capping layer in order to form a trench (410) aligned to the gate metal in the electrically insulating layer; and filling the trench with an electrically insulating material in order to form an electrically insulating cap (150) centered on the gate metal.

Abstract: A method of manufacturing a metal gate structure includes providing a substrate (110) having formed thereon a gate dielectric (120), a work function metal (130) adjacent to the gate dielectric, and a gate metal (140) adjacent to the work function metal; selectively forming a sacrificial capping layer (310) centered over the gate metal; forming an electrically insulating layer (161) over the sacrificial capping layer such that the electrically insulating layer at least partially surrounds the sacrificial capping layer; selectively removing the sacrificial capping layer in order to form a trench (410) aligned to the gate metal in the electrically insulating layer; and filling the trench with an electrically insulating material in order to form an electrically insulating cap (150) centered on the gate metal.

Abstract: A microelectronic device includes a metal gate with a metal gate upper surface. The metal gate is disposed in an interlayer dielectric first layer. The interlayer dielectric first layer also has an upper surface that is coplanar with the metal gate upper surface. A dielectric etch stop layer is disposed on the metal gate upper surface but not on the interlayer dielectric first layer upper surface.

Abstract: Methods to selectively form a dielectric etch stop layer over a patterned metal feature. Embodiments include a transistor incorporating such an etch stop layer over a gate electrode. In accordance with certain embodiments of the present invention, a metal is selectively formed on the surface of the gate electrode which is then converted to a silicide or germanicide. In other embodiments, the metal selectively formed on the gate electrode surface enables a catalytic growth of a silicon or germanium mesa over the gate electrode. At least a portion of the silicide, germanicide, silicon mesa or germanium mesa is then oxidized, nitridized, or carbonized to form a dielectric etch stop layer over the gate electrode only.

Abstract: A microelectronic device includes a metal gate with a metal gate upper surface. The metal gate is disposed in an interlayer dielectric first layer. The interlayer dielectric first layer also has an upper surface that is coplanar with the metal gate upper surface. A dielectric etch stop layer is disposed on the metal gate upper surface but not on the interlayer dielectric first layer upper surface.

Abstract: Methods to selectively form a dielectric etch stop layer over a patterned metal feature. Embodiments include a transistor incorporating such an etch stop layer over a gate electrode. In accordance with certain embodiments of the present invention, a metal is selectively formed on the surface of the gate electrode which is then converted to a silicide or germanicide. In other embodiments, the metal selectively formed on the gate electrode surface enables a catalytic growth of a silicon or germanium mesa over the gate electrode. At least a portion of the silicide, germanicide, silicon mesa or germanium mesa is then oxidized, nitridized, or carbonized to form a dielectric etch stop layer over the gate electrode only.

Abstract: A method of manufacturing a metal gate structure includes providing a substrate (110) having formed thereon a gate dielectric (120), a work function metal (130) adjacent to the gate dielectric, and a gate metal (140) adjacent to the work function metal; selectively forming a sacrificial capping layer (310) centered over the gate metal; forming an electrically insulating layer (161) over the sacrificial capping layer such that the electrically insulating layer at least partially surrounds the sacrificial capping layer; selectively removing the sacrificial capping layer in order to form a trench (410) aligned to the gate metal in the electrically insulating layer; and filling the trench with an electrically insulating material in order to form an electrically insulating cap (150) centered on the gate metal.

Abstract: Interconnect structures having improved adhesion and electromigration performance and methods to fabricate thereof are described. A tensile capping layer is formed on a first conductive layer on a substrate. A compressive capping layer is formed on the tensile capping layer. Next, an interlayer dielectric layer is formed on the compressive capping layer. Further, a first opening is formed in the ILD layer using a first chemistry. A second opening is formed in the tensile capping layer and the compressive capping layer using a second chemistry. Next, a second conductive layer is formed in the first opening and the second opening.

Abstract: The present invention provides a method for growing atomic layer thin films on functionalized substrates at room temperature using catalyzed binary reaction sequence chemistry. Specifically, the atomic layer films are grown using two half-reactions. Catalysts are used to activate surface species in both half-reactions thereby enabling both half-reactions to be carried out at room temperature.