Abstract: The described technology provides a method including receiving a request from an agent for accessing a cogran and for allocating an agent ID to one of a plurality of SFT entries in a snoop filter (SFT), performing a tag lookup function for a tag of the cogran in the SFT to find a matched SFT entry, wherein the matched SFT entry is tracking the tag of the cogran, determining the number n of agents being tracked by the matched SFT entry, and in response to determining that the number n of agents being tracked by the matched entry is above a threshold, storing a DVT index in the tracking_info field of the matched SFT entry, wherein the DVT index selects a DVT entry in a disaggregated vector table (DVT), wherein the selected DVT entry is configured to hold a tracking vector for tracking the agents that have cached the cogran for the matched SFT entry.

Abstract: Systems and methods for effective set sampling and set-dueling in large distributed system level caches are described. An example method includes a shared cache instance (SCI), from among a plurality of SCIs, receiving a request associated with a thread, where the request comprises policy information for specifying at least one of two cache algorithms for implementation by the SCI for any requests associated with the thread. The method further includes the SCI implementing the at least one of the two cache algorithms specified by the policy information received as part of the request associated with the thread unless the SCI is identified as a delegated shared cache instance, from among the SCIs, for determining a winner between the two cache algorithms for use with any requests associated with the thread.

Abstract: Embodiments of the present disclosure include techniques for managing dirty data. An agent receives a request for data. If the data is dirty data, the agent may use a replacement policy to determine if the data should be passed clean or dirty to the requestor. The replacement policy may correspond to how long the dirty data being stored in a cache line is to be maintained. In one embodiment, the replacement policy is a circuit, such as an SRAM and a logic circuit, for example.

Abstract: A low latency cache intervention mechanism implements a snoop filter to dynamically select an intervener cache for a cache “hit” in a multiprocessor architecture of a computer system. The selection of the intervener is based on variables such as latency, topology, frequency, utilization, load, wear balance, and/or power state of the computer system.

Abstract: Efficient techniques are described for controlling ordered accesses in a weakly ordered storage system. A stream of memory requests is split into two or more streams of memory requests and a memory access counter is incremented for each memory request. A memory request requiring ordered memory accesses is identified in one of the two or more streams of memory requests. The memory request requiring ordered memory accesses is stalled upon determining a previous memory request from a different stream of memory requests is pending. The memory access counter is decremented for each memory request guaranteed to complete. A count value in the memory access counter that is different from an initialized state of the memory access counter indicates there are pending memory requests. The memory request requiring ordered memory accesses is processed upon determining there are no further pending memory requests.

Abstract: The content and order of a predetermined sequence of hard-coded and/or quasi-programmable test patterns may be altered during a Built-In Self-Test (BIST) routine. As such, knowledge gained post design completion may be reflected in the selection and arrangement of available tests to be executed during a BIST routine. In one embodiment, a sequence of hard-coded and/or quasi-programmable tests is executed during a BIST routine by receiving test ordering information for the sequence of tests and executing the sequence of tests in an order indicated by the test ordering information. A corresponding BIST circuit comprises a storage element and a state machine. The storage element is configured to store test ordering information for the sequence of tests. The state machine is configured to execute the sequence of tests in an order indicated by the test ordering information.

Abstract: Efficient techniques are described for controlling ordered accesses in a weakly ordered storage system. A stream of memory requests is split into two or more streams of memory requests and a memory access counter is incremented for each memory request. A memory request requiring ordered memory accesses is identified in one of the two or more streams of memory requests. The memory request requiring ordered memory accesses is stalled upon determining a previous memory request from a different stream of memory requests is pending. The memory access counter is decremented for each memory request guaranteed to complete. A count value in the memory access counter that is different from an initialized state of the memory access counter indicates there are pending memory requests. The memory request requiring ordered memory accesses is processed upon determining there are no further pending memory requests.

Abstract: The content and order of a predetermined sequence of hard-coded and/or quasi-programmable test patterns may be altered during a Built-In Self-Test (BIST) routine. As such, knowledge gained post design completion may be reflected in the selection and arrangement of available tests to be executed during a BIST routine. In one embodiment, a sequence of hard-coded and/or quasi-programmable tests is executed during a BIST routine by receiving test ordering information for the sequence of tests and executing the sequence of tests in an order indicated by the test ordering information. A corresponding BIST circuit comprises a storage element and a state machine. The storage element is configured to store test ordering information for the sequence of tests. The state machine is configured to execute the sequence of tests in an order indicated by the test ordering information.