Patents by Inventor Jason Luo Pang

Jason Luo Pang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11029749
    Abstract: In one embodiment, a system includes a number of application-specific integrated circuits (ASICs). At least one of the ASICs is configured to process incoming data packets and outgoing data packets. At least one of the ASICs is configured to move data between a respective networking module and a destination networking module. The system also includes a cable backplane having a number of parallel cables configured to transmit data between the number of ASICs.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: June 8, 2021
    Assignee: Platina Systems Corp.
    Inventors: Frank Szu-Jen Yang, Jason Luo Pang, Mark Tehmin Yin
  • Patent number: 10416752
    Abstract: In one embodiment, a system includes a number of application-specific integrated circuits (ASICs). The system also includes one or more processors coupled to the ASICs including instructions executable by the processors. The processors being operable when executing the instructions to configure the plurality of ASICs to route data packets using a standard protocol; configure the ASICs to set up a tunnel, using the standard protocol, for moving data packets from one ASIC to another of the number of ASICs; and implement a software overlay to facilitate interaction between the number of ASICs through the tunnel for moving the data packets.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: September 17, 2019
    Assignee: Platina Systems Corporation
    Inventors: Frank Szu-Jen Yang, Jason Luo Pang, Eliot Michael Dresselhaus, Dino Farinacci, Andreas Demetrios Bovopoulos, Mark Tehmin Yin
  • Patent number: 10386913
    Abstract: In one embodiment, a system includes a number of networking modules. Each module includes a respective voltage controller and a voltage-configuration circuit. The voltage-configuration circuit includes a number of transistors that are each coupled to a respective resistor. The system also includes one or more processors coupled to the voltage controllers including instructions executable by the processors. The processors being operable when executing the instructions to configure, for each module, an on-state or off-state of the transistors coupled to the respective resistor. The transistors coupled to the respective resistor correspond to a bit of a number of under-voltage thresholds. The processors are also operable to preset, during a module initialization, a relative ranking of under-voltage shutdown between the modules by setting the transistors. At least one of the number of networking modules has a different under-voltage threshold level relative to another one of the networking modules.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: August 20, 2019
    Assignee: Platina Systems Corporation
    Inventors: Frank Szu-Jen Yang, Jason Luo Pang
  • Publication number: 20190056776
    Abstract: In one embodiment, a system includes a number of application-specific integrated circuits (ASICs). The system also includes one or more processors coupled to the ASICs including instructions executable by the processors. The processors being operable when executing the instructions to configure the plurality of ASICs to route data packets using a standard protocol; configure the ASICs to set up a tunnel, using the standard protocol, for moving data packets from one ASIC to another of the number of ASICs; and implement a software overlay to facilitate interaction between the number of ASICs through the tunnel for moving the data packets.
    Type: Application
    Filed: October 22, 2018
    Publication date: February 21, 2019
    Inventors: Frank Szu-Jen Yang, Jason Luo Pang, Eliot Michael Dresselhaus, Dino Farinacci, Andreas Demetrios Bovopoulos, Mark Tehmin Yin
  • Patent number: 10139894
    Abstract: In one embodiment, a system includes a number of application-specific integrated circuits (ASICs). The system also includes one or more processors coupled to the ASICs including instructions executable by the processors. The processors being operable when executing the instructions to configure the plurality of ASICs to route data packets using a standard protocol; configure the ASICs to set up a tunnel, using the standard protocol, for moving data packets from one ASIC to another of the number of ASICs; and implement a software overlay to facilitate interaction between the number of ASICs through the tunnel for moving the data packets.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: November 27, 2018
    Assignee: Platina Systems Corp.
    Inventors: Frank Szu-Jen Yang, Jason Luo Pang, Eliot Michael Dresselhaus, Dino Farinacci, Andreas Demetrios Bovopoulos, Mark Tehmin Yin
  • Publication number: 20170289029
    Abstract: In one embodiment, a system includes a number of application-specific integrated circuits (ASICs). The system also includes one or more processors coupled to the ASICs including instructions executable by the processors. The processors being operable when executing the instructions to configure the plurality of ASICs to route data packets using a standard protocol; configure the ASICs to set up a tunnel, using the standard protocol, for moving data packets from one ASIC to another of the number of ASICs; and implement a software overlay to facilitate interaction between the number of ASICs through the tunnel for moving the data packets.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 5, 2017
    Inventors: Frank Szu-Jen Yang, Jason Luo Pang, Thomas M. Grennan, Eliot Michael Dresselhaus, Dino Farinacci, Andreas Demetrios Bovopoulos, Mark Tehmin Yin
  • Publication number: 20170286339
    Abstract: In one embodiment, a system includes a number of application-specific integrated circuits (ASICs). At least one of the ASICs is configured to process incoming data packets and outgoing data packets. At least one of the ASICs is configured to move data between a respective networking module and a destination networking module. The system also includes a cable backplane having a number of parallel cables configured to transmit data between the number of ASICs.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 5, 2017
    Inventors: Frank Szu-Jen Yang, Jason Luo Pang, Mark Tehmin Yin
  • Publication number: 20170285729
    Abstract: In one embodiment, a system includes a number of networking modules. Each module includes a respective voltage controller and a voltage-configuration circuit. The voltage-configuration circuit includes a number of transistors that are each coupled to a respective resistor. The system also includes one or more processors coupled to the voltage controllers including instructions executable by the processors. The processors being operable when executing the instructions to configure, for each module, an on-state or off-state of the transistors coupled to the respective resistor. The transistors coupled to the respective resistor correspond to a bit of a number of under-voltage thresholds. The processors are also operable to preset, during a module initialization, a relative ranking of under-voltage shutdown between the modules by setting the transistors. At least one of the number of networking modules has a different under-voltage threshold level relative to another one of the networking modules.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 5, 2017
    Inventors: Frank Szu-Jen Yang, Jason Luo Pang