Abstract: A method, system and computer program product for enabling a register file to recover from detection of a parity error. A first register file and a second register file are associated with a parallel file structure. When the parity error is detected, the system determines whether the first register file or second register file is associated with the parity error. The register file determined to have the parity error is associated with an offending register and a non-offending register is associated with the “good” register file. Subsequent to the detection of the parity error, the system executes a repair sequence, whereby the register file associated with the offending register receives data from the register file associated with the non-offending register. The offending register file recovers from the parity error with or without the use of a parity interrupt.

Abstract: A method, system and computer program product for enabling a register file to recover from detection of a parity error. A first register file and a second register file are associated with a parallel file structure. When the parity error is detected, the system determines whether the first register file or second register file is associated with the parity error. The register file determined to have the parity error is associated with an offending register and a non-offending register is associated with the “good” register file. Subsequent to the detection of the parity error, the system executes a repair sequence, whereby the register file associated with the offending register receives data from the register file associated with the non-offending register. The offending register file recovers from the parity error with or without the use of a parity interrupt.

Abstract: The present invention comprise methods and systems for enforcing allowable hardware configurations. The present invention utilizes shadow registers, which act as gatekeepers for actual sensitive configuration registers. An attempted write to the actual sensitive configuration registers is first stored in a corresponding shadow register and is subsequently validated via a cryptographic hash register before the values are passed to the actual configuration register.

Abstract: Management of hierarchical identifiers in simulation models and netlists is accomplished using a prefix compressor algorithm running on a general purpose computer processor. Full name compression is accomplished when hierarchy data and remainder data are split off and prefix compressed. Compressing prefixes of names in the hierarchy list is performed by comparing a previous entry to a current entry. Compressing prefixes of names in the name list is performed by running an output of compressing of prefixes of names in the hierarchy list and running an output of the compressing of prefixes of names in the name list through a standard compressor software application package. Decompressing of names uses sub operations inverse to the prefix compressor algorithm. The decompressing sub operations create a string pointed to by the prefix pointer and concatenated onto the string pointed to by the name pointer; and thus a full name is created.