Patents by Inventor Jason Ma

Jason Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12261571
    Abstract: A system includes a reference field effect transistor (FET), wherein the reference FET is a depletion mode transistor, and a bias control circuit. The bias control circuit includes a voltage sensor connected to a drain terminal of the reference FET. The voltage sensor is configured to measure a voltage at the drain terminal of the reference FET as a measured voltage, determine a voltage difference between a reference voltage and the measured voltage, and output the voltage difference at a voltage sensor output terminal. The system includes a translation circuit connected the voltage sensor output terminal. The translation circuit is configured to convert the voltage difference into a negative gate bias voltage, and apply the negative gate bias voltage to a gate terminal of the reference FET.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: March 25, 2025
    Assignee: NXP USA, Inc.
    Inventors: Elie A. Maalouf, Xu Jason Ma
  • Patent number: 12248671
    Abstract: Embodiments of the present disclosure relate to user interfaces and systems that may enable dynamic and interactive access of, investigation of, and analysis of data objects stored in one or more databases. The data objects may be accessed from the one or more databases, and presented in multiple related portions of a display. In particular, the system provides a time-based visualization of data objects (and/or properties associated with the data objects) to a user such that the user may, for example, determine connections between various data objects, observe flows of information among data objects, and/or investigate related data objects.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: March 11, 2025
    Assignee: Palantir Technologies Inc.
    Inventors: Jason Ma, Aaron Davidson
  • Patent number: 12217091
    Abstract: System and method for terminating instances and autoscaling instance groups of computing platforms. For example, a method includes determining whether an instance of an instance group is identified as eligible for termination. The method further includes, in response to determining that the instance of the instance group is identified as eligible for termination, terminating the eligible instance. The terminating the eligible instance includes, in response to a runtime of the eligible instance being equal to or larger than a predetermined maximum lifetime, terminating the eligible instance.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: February 4, 2025
    Assignee: Palantir Technologies Inc.
    Inventors: Mahmoud Abdelsalam, Ryan McNamara, Ashray Jain, Greg DeArment, Jason Ma, Guodong Xu, Vivek Lakshmanan
  • Publication number: 20240364277
    Abstract: An amplifier device, such as an operational amplifier device or unity gain buffer, may include a first input terminal, an inverting input terminal, a non-inverting input terminal, a reference voltage supply terminal, a negative voltage supply terminal, and an output terminal. The amplifier device may include one or more cascode arrangements, such as a first cascode arrangement coupled between the negative voltage supply terminal and the output terminal. A first transistor of the first cascode stage may be configured to receive a variable bias voltage at its gate terminal. A second transistor of the first cascode stage may be configured to receive a fixed bias voltage at its gate terminal. The variable bias voltage may correspond to a first input voltage supplied at the first input terminal.
    Type: Application
    Filed: April 28, 2023
    Publication date: October 31, 2024
    Inventors: David Edward Bien, Xu Jason Ma
  • Patent number: 12132473
    Abstract: A switching device may include an input terminal, an output terminal, a primary switching transistor electrically coupled between the input terminal and the output terminal, and a cascode arrangement electrically coupled between the primary switching transistor and the input terminal. The cascode arrangement may include multiple cascode transistors, each having gate terminals coupled to nodes of a voltage divider that is coupled between a positive voltage supply and a reference voltage supply. Emitter-follower bipolar junction transistors (BJTs) may be configured to control voltages at the gate terminals of the primary switching transistor and the cascode transistors to accommodate changes in the output voltage at the output terminal.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: October 29, 2024
    Assignee: NXP USA, Inc.
    Inventors: David Edward Bien, Xu Jason Ma
  • Patent number: 12126338
    Abstract: A switching device may include an input terminal, an output terminal, a primary switching transistor coupled between the input terminal and the output terminal, logic circuitry configured to receive a control signal to selectively activate the switching device, a first cascode arrangement coupled between the logic circuitry and a first reference voltage supply, and a second cascode arrangement coupled between the input terminal and the primary switching transistor. The first cascode arrangement may include cascode transistors having gate terminals coupled to a first voltage divider coupled between the first reference voltage supply and a second reference voltage supply that is coupled to the logic circuitry. The second cascode arrangement may include a first cascode transistor coupled to a fixed voltage at the first voltage divider and second and third cascode transistors coupled to variable cascode bias voltages at a second voltage divider coupled to a variable voltage input.
    Type: Grant
    Filed: April 4, 2023
    Date of Patent: October 22, 2024
    Assignee: NXP USA, Inc.
    Inventors: David Edward Bien, Xu Jason Ma
  • Publication number: 20240340011
    Abstract: A switching device may include an input terminal, an output terminal, a primary switching transistor coupled between the input terminal and the output terminal, logic circuitry configured to receive a control signal to selectively activate the switching device, a first cascode arrangement coupled between the logic circuitry and a first reference voltage supply, and a second cascode arrangement coupled between the input terminal and the primary switching transistor. The first cascode arrangement may include cascode transistors having gate terminals coupled to a first voltage divider coupled between the first reference voltage supply and a second reference voltage supply that is coupled to the logic circuitry. The second cascode arrangement may include a first cascode transistor coupled to a fixed voltage at the first voltage divider and second and third cascode transistors coupled to variable cascode bias voltages at a second voltage divider coupled to a variable voltage input.
    Type: Application
    Filed: April 4, 2023
    Publication date: October 10, 2024
    Inventors: David Edward Bien, Xu Jason Ma
  • Publication number: 20240313762
    Abstract: A switching device may include an input terminal, an output terminal, a primary switching transistor electrically coupled between the input terminal and the output terminal, and a cascode arrangement electrically coupled between the primary switching transistor and the input terminal. The cascode arrangement may include multiple cascode transistors, each having gate terminals coupled to nodes of a voltage divider that is coupled between a positive voltage supply and a reference voltage supply. Emitter-follower bipolar junction transistors (BJTs) may be configured to control voltages at the gate terminals of the primary switching transistor and the cascode transistors to accommodate changes in the output voltage at the output terminal.
    Type: Application
    Filed: March 13, 2023
    Publication date: September 19, 2024
    Inventors: David Edward Bien, Xu Jason Ma
  • Patent number: 11895137
    Abstract: Embodiments of the present disclosure relate to a data analysis system that may automatically generate memory-efficient clustered data structures, automatically analyze those clustered data structures, and provide results of the automated analysis in an optimized way to an analyst. The automated analysis of the clustered data structures (also referred to herein as data clusters) may include an automated application of various criteria or rules so as to generate a compact, human-readable analysis of the data clusters. The human-readable analyses (also referred to herein as “summaries” or “conclusions”) of the data clusters may be organized into an interactive user interface so as to enable an analyst to quickly navigate among information associated with various data clusters and efficiently evaluate those data clusters in the context of, for example, a fraud investigation. Embodiments of the present disclosure also relate to automated scoring of the clustered data structures.
    Type: Grant
    Filed: December 2, 2022
    Date of Patent: February 6, 2024
    Assignee: Palantir Technologies Inc.
    Inventors: David Cohen, Jason Ma, Bing Jie Fu, Ilya Nepomnyashchiy, Steven Berler, Alex Smaliy, Jack Grossman, James Thompson, Julia Boortz, Matthew Sprague, Parvathy Menon, Michael Kross, Michael Harris, Adam Borochoff
  • Patent number: 11892901
    Abstract: Disclosed are data gathering and analysis systems, methods, and computer-readable storage media to facilitate an investigation process. The method includes accessing a data object representing an investigative issue as part of initiating an investigative session. The method further includes causing presentation, on a display of a device, of a user interface configured to receive user search queries and present search results for each received search query. The method further includes tracking user activity including one or more user actions performed during the investigative session. The method further includes creating a record of the user activity, and linking the record of the user activity with the data object representing the investigative issue.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: February 6, 2024
    Assignee: Palantir Technologies Inc.
    Inventors: David Skiff, Allen Cai, Benjamin Lee, Christopher Yu, Hind Kraytem, Jason Ma, Myles Scolnick, Tarik Benabdallah, Zhixian Shen
  • Patent number: 11789931
    Abstract: Systems are provided for managing defect data objects. A system stores a plurality of defect data objects that have been input to the system, and generates an issue item including one or more defect data objects that are selected from the stored defect data objects based on user input. The system determines similarity between the one or more defect data objects in the issue item and one or more of the stored defect data objects that are out of the issue item, based on comparison of one or more parameter values. The system determines one or more candidate defect data objects to be included in the issue item from the one or more of the stored defect data objects that are out of the issue item based on the similarity, and includes one or more of the determined candidate defect data objects in the issue item based on user input.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: October 17, 2023
    Assignee: Palantir Technologies Inc.
    Inventors: Jason Ma, Allen Cai, Andrew Cooper, Arnaud Drizard, Benjamin Lee, Damien Cramard, Damian Rusak, Hind Kraytem, Jan Matas, Ludovic Lay, Myles Scolnick, Radu-Andrei Szasz, Stefan Negrus, Taylor Cathcart, Zhixian Shen
  • Publication number: 20230308052
    Abstract: A system includes a reference field effect transistor (FET), wherein the reference FET is a depletion mode transistor, and a bias control circuit. The bias control circuit includes a voltage sensor connected to a drain terminal of the reference FET. The voltage sensor is configured to measure a voltage at the drain terminal of the reference FET as a measured voltage, determine a voltage difference between a reference voltage and the measured voltage, and output the voltage difference at a voltage sensor output terminal. The system includes a translation circuit connected the voltage sensor output terminal. The translation circuit is configured to convert the voltage difference into a negative gate bias voltage, and apply the negative gate bias voltage to a gate terminal of the reference FET.
    Type: Application
    Filed: March 28, 2022
    Publication date: September 28, 2023
    Inventors: Elie A. Maalouf, Xu Jason Ma
  • Publication number: 20230299720
    Abstract: An amplifier system includes an amplifier transistor and a reference transistor used to provide a direct current (DC) bias voltage to bias a gate terminal of the amplifier transistor. The amplifier transistor may have a drain terminal coupled to a drain voltage supply and a radio frequency (RF) output node and a gate terminal coupled to bias circuitry that includes the reference transistor. The reference transistor may have a gate terminal coupled to a reference potential, a drain terminal coupled to the drain voltage supply, and a source terminal coupled to a constant current source and to the gate terminal of the amplifier transistor. The reference transistor may be formed on the same die as the amplifier transistor and may have a threshold voltage that is correlated with that of the amplifier transistor.
    Type: Application
    Filed: March 15, 2022
    Publication date: September 21, 2023
    Inventors: Elie A. Maalouf, Ngai-Ming Lau, Xu Jason Ma
  • Patent number: 11742809
    Abstract: Embodiments of a device and method are disclosed. In an embodiment, a current sensing circuit includes first and second integrated resistors on a semiconductor die, a controllable current source configured to provide a reference current, and a current determination circuit. A resistance value of the second integrated resistor is a factor n larger than a resistance value of the first integrated resistor. A current drawn by a target circuit is configured to flow through the first integrated resistor, and the reference current is configured to flow through the second integrated resistor. The current determination circuit is configured to determine a value of the current drawn by the target circuit based on the value of the reference current when a first voltage at a terminal of the first integrated resistor is approximately equal to a second voltage at a terminal of the second integrated resistor.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: August 29, 2023
    Assignee: NXP USA, Inc.
    Inventors: Elie A. Maalouf, Xu Jason Ma
  • Patent number: 11727481
    Abstract: Embodiments of the present disclosure relate to a data analysis system that may automatically generate memory-efficient clustered data structures, automatically analyze those clustered data structures, automatically tag and group those clustered data structures, and provide results of the automated analysis and grouping in an optimized way to an analyst. The automated analysis of the clustered data structures (also referred to herein as data clusters) may include an automated application of various criteria or rules so as to generate a tiled display of the groups of related data clusters such that the analyst may quickly and efficiently evaluate the groups of data clusters. In particular, the groups of data clusters may be dynamically re-grouped and/or filtered in an interactive user interface so as to enable an analyst to quickly navigate among information associated with various groups of data clusters and efficiently evaluate those data clusters in the context of, for example, a fraud investigation.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: August 15, 2023
    Assignee: Palantir Technologies Inc.
    Inventors: Alexander Visbal, James Thompson, Marvin Sum, Jason Ma, Bing Jie Fu, Ilya Nepomnyashchiy, Devin Witherspoon, Victoria Lai, Steven Berler, Alexei Smaliy, Suchan Lee
  • Patent number: 11689100
    Abstract: Aspects of the subject disclosure may include, for example, obtaining, by a first circuit of a charge pump circuit, charge sourced from a power supply operative at a first voltage level, wherein the first circuit comprises a first plurality of transistors, and wherein each of the first plurality of transistors is rated for operation at an applied voltage that is less than the first voltage level, storing the charge in a first capacitor of the first circuit at a first point in time, and transferring the charge stored in the first capacitor to a second capacitor of a second circuit of the charge pump circuit at a second point in time such that the second capacitor stores the charge, wherein the second point in time is subsequent to the first point in time. Other embodiments are disclosed.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: June 27, 2023
    Assignee: NXP USA, Inc.
    Inventors: Mohammad Nizam Kabir, Madan Mohan Reddy Vemula, Xu Jason Ma
  • Publication number: 20230096596
    Abstract: Embodiments of the present disclosure relate to a data analysis system that may automatically generate memory-efficient clustered data structures, automatically analyze those clustered data structures, and provide results of the automated analysis in an optimized way to an analyst. The automated analysis of the clustered data structures (also referred to herein as data clusters) may include an automated application of various criteria or rules so as to generate a compact, human-readable analysis of the data clusters. The human-readable analyses (also referred to herein as “summaries” or “conclusions”) of the data clusters may be organized into an interactive user interface so as to enable an analyst to quickly navigate among information associated with various data clusters and efficiently evaluate those data clusters in the context of, for example, a fraud investigation. Embodiments of the present disclosure also relate to automated scoring of the clustered data structures.
    Type: Application
    Filed: December 2, 2022
    Publication date: March 30, 2023
    Inventors: David Cohen, Jason Ma, Bing Jie Fu, Ilya Nepomnyashchiy, Steven Berler, Alex Smaliy, Jack Grossman, James Thompson, Julia Boortz, Matthew Sprague, Parvathy Menon, Michael Kross, Michael Harris, Adam Borochoff
  • Publication number: 20230043703
    Abstract: The subject invention pertains to the detection and differentiation of genetic variations by nucleic acid amplification. The invention provides methods of detecting one or more genetic variations in a nucleic acid that are in close proximity simultaneously. The invention further provides primer and probe oligonucleotides and methods of using said primers and probes in assays to detect genetic variants of concern of SARS-CoV-2. The methods of the invention detect genetic variants of other pathogens, including influenza, or genetic variants involved in inheritable diseases or cancer.
    Type: Application
    Filed: July 21, 2022
    Publication date: February 9, 2023
    Inventors: YAN WANG, STEVEN TAKASHI OKINO, JASON MA
  • Publication number: 20230015111
    Abstract: Aspects of the subject disclosure may include, for example, obtaining, by a first circuit of a charge pump circuit, charge sourced from a power supply operative at a first voltage level, wherein the first circuit comprises a first plurality of transistors, and wherein each of the first plurality of transistors is rated for operation at an applied voltage that is less than the first voltage level, storing the charge in a first capacitor of the first circuit at a first point in time, and transferring the charge stored in the first capacitor to a second capacitor of a second circuit of the charge pump circuit at a second point in time such that the second capacitor stores the charge, wherein the second point in time is subsequent to the first point in time. Other embodiments are disclosed.
    Type: Application
    Filed: July 15, 2021
    Publication date: January 19, 2023
    Applicant: NXP USA, Inc.
    Inventors: Mohammad Nizam Kabir, Madan Mohan Reddy Vemula, Xu Jason Ma
  • Patent number: 11546364
    Abstract: Embodiments of the present disclosure relate to a data analysis system that may automatically generate memory-efficient clustered data structures, automatically analyze those clustered data structures, and provide results of the automated analysis in an optimized way to an analyst. The automated analysis of the clustered data structures (also referred to herein as data clusters) may include an automated application of various criteria or rules so as to generate a compact, human-readable analysis of the data clusters. The human-readable analyses (also referred to herein as “summaries” or “conclusions”) of the data clusters may be organized into an interactive user interface so as to enable an analyst to quickly navigate among information associated with various data clusters and efficiently evaluate those data clusters in the context of, for example, a fraud investigation. Embodiments of the present disclosure also relate to automated scoring of the clustered data structures.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: January 3, 2023
    Assignee: Palantir Technologies Inc.
    Inventors: David Cohen, Jason Ma, Bing Jie Fu, Ilya Nepomnyashchiy, Steven Berler, Alex Smaliy, Jack Grossman, James Thompson, Julia Boortz, Matthew Sprague, Parvathy Menon, Michael Kross, Michael Harris, Adam Borochoff