Abstract: A bicycle includes a frame, a front and rear wheel and a crank assembly. The frame includes chainstays and a bottom bracket having a center and which rotationally receives the crank assembly. The crank assembly includes a chain ring having a radius between the bottom bracket center and a circumferential edge. The chainstays are connected to the bottom bracket at a first end and rotationally receive the rear wheel at a second end. The chainstay defines a cutout sized to receive a portion of a circumferential edge of the chain ring.

Abstract: In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure and a second device receiving structure and a contact extension that is common to the first and second device receiving structures. The first device receiving structure includes a device receiving area and the second device receiving structure includes a drain contact area. A III-N based semiconductor chip has a drain bond pad bonded to the drain contact area and a source bond pad bonded to the contact extension and a gate bond pad bonded to an interconnect. A portion of the silicon based semiconductor chip is bonded to the support device receiving area. In accordance with another embodiment, a method for manufacturing the semiconductor component includes coupling a III-N based semiconductor chip to a portion of the support a silicon based semiconductor chip to another portion of the support.

Abstract: A cascode switch structure includes a group III-V transistor structure having a first current carrying electrode, a second current carrying electrode and a first control electrode. A semiconductor MOSFET device includes a third current carrying electrode electrically connected to the second current carrying electrode, a fourth current carrying electrode electrically connected to the first control electrode, and a second control electrode. A first diode includes a first cathode electrode electrically connected to the first current carrying electrode and a first anode electrode. A second diode includes a second anode electrode electrically connected to the first anode electrode and a second cathode electrode electrically connected to the fourth current carrying electrode. In one embodiment, the group III-V transistor structure, the first diode, and the second diode are integrated within a common substrate.

Abstract: In one embodiment, a cascode rectifier structure includes a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A rectifier device is integrated with the group III-V semiconductor structure and is electrically connected to the first current carrying electrode and to a third electrode. The control electrode is further electrically connected to the semiconductor substrate and the second current path is generally perpendicular to a primary current path between the first and second current carrying electrodes. The cascode rectifier structure is configured as a two terminal device.

Abstract: A half-bridge circuit can include a high-side HEMT, a high-side switch transistor, a low-side HEMT, and a low-side switch transistor. The die substrates of the HEMTs can be coupled to the sources of their corresponding switch transistors. In another aspect, a packaged electronic device for a half-bridge circuit can have a design that can use shorter connectors that help to reduce parasitic inductance and resistance. In a further aspect, a packaged electronic device for a half-bridge circuit can include more than one connection along the bottom of the package allows less lead connections along the periphery of the packaged electronic device and can allow for a smaller package.

Abstract: A linear fader includes a slider that is configured to slide along a rail. The slider includes a magnet. The linear fader also includes a plurality of coils spaced along a length of the rail, one or more sensors configured to detect a position of the slider along the rail, and control circuitry operatively coupled to the plurality of coils and the one or more sensors. The control circuitry is configured to receive a signal corresponding to a first location of the slider from at least one of the one or more sensors, receive a desired location of the slider, and cause a first electrical current to pass through the plurality of coils, thereby generating a force on the slider in a direction toward the desired location.

Abstract: Aspects of the present disclosure describe methods and apparatuses that hide latency during an interaction between an attacking client device platform and a defending client device platform in a multiplayer game played over a network. The attacking client device platform predicts a successful attack will be made and delivers a hit event to the defending client device platform. In order to provide additional time to wait for a hit reply from the defending client device platform the attacking client device platform initiates an altered animation mode that lengthens the run-time of the animation. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: In one embodiment, a group III-V transistor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A clamping device is integrated with the group III-V transistor structure and is electrically connected to the first current carrying electrode a third electrode to provide a secondary current path during, for example, an electrical stress event.

Abstract: In one embodiment, a cascode rectifier structure includes a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A rectifier device is integrated with the group III-V semiconductor structure and is electrically connected to the first current carrying electrode and to a third electrode. The control electrode is further electrically connected to the semiconductor substrate and the second current path is generally perpendicular to a primary current path between the first and second current carrying electrodes.

Abstract: Aspects of the present disclosure describe methods and apparatuses that hide latency during an interaction between an attacking client device platform and a defending client device platform in a multiplayer game played over a network. The attacking client device platform predicts a successful attack will be made and delivers a hit event to the defending client device platform. In order to provide additional time to wait for a hit reply from the defending client device platform the attacking client device platform initiates an altered animation mode that lengthens the run-time of the animation. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure and a second device receiving structure and a contact extension that is common to the first and second device receiving structures. The first device receiving structure includes a device receiving area and the second device receiving structure includes a drain contact area. A III-N based semiconductor chip has a drain bond pad bonded to the drain contact area and a source bond pad bonded to the contact extension and a gate bond pad bonded to an interconnect. A portion of the silicon based semiconductor chip is bonded to the support device receiving area. In accordance with another embodiment, a method for manufacturing the semiconductor component includes coupling a III-N based semiconductor chip to a portion of the support a silicon based semiconductor chip to another portion of the support.

Abstract: A half-bridge circuit can include a high-side HEMT, a high-side switch transistor, a low-side HEMT, and a low-side switch transistor. The die substrates of the HEMTs can be coupled to the sources of their corresponding switch transistors. In another aspect, a packaged electronic device for a half-bridge circuit can have a design that can use shorter connectors that help to reduce parasitic inductance and resistance. In a further aspect, a packaged electronic device for a half-bridge circuit can include more than one connection along the bottom of the package allows less lead connections along the periphery of the packaged electronic device and can allow for a smaller package.

Abstract: A bicycle includes a frame, a front and rear wheel and a crank assembly. The frame includes chainstays and a bottom bracket having a center and which rotationally receives the crank assembly. The crank assembly includes a chain ring having a radius between the bottom bracket center and a circumferential edge. The chainstays are connected to the bottom bracket at a first end and rotationally receive the rear wheel at a second end. The chainstay defines a cutout sized to receive a portion of a circumferential edge of the chain ring.

Abstract: In one embodiment, a cascode rectifier structure includes a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A rectifier device is integrated with the group III-V semiconductor structure and is electrically connected to the first current carrying electrode and to a third electrode. The control electrode is further electrically connected to the semiconductor substrate and the second current path is generally perpendicular to a primary current path between the first and second current carrying electrodes.

Abstract: In one embodiment, a group III-V transistor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A clamping device is integrated with the group III-V transistor structure and is electrically connected to the first current carrying electrode a third electrode to provide a secondary current path during, for example, an electrical stress event.

Abstract: A rotary fader apparatus includes a fader control knob that is directly attached to the rotor of a non-contact electrical motor. The apparatus may produce a fade effect based on the rotational position of the fader control knob and may be automated through signals to the motor. Such a rotary fader apparatus may be used, for example, in audio mixing applications to provide automated or manual rotary control of track fading. The motor may also be used to alter the feel of the movement of the fader control knob and/or provide tactile feedback in response to mixing parameters or signal properties.

Abstract: Systems, methods, and other embodiments associated with and\ adaptive data model and warehouse palette are provided. In one embodiment, a method includes providing a user interface for collecting item definition attributes from a user. A database structure is generated to store item data according to collected the item definition attributes. An extract, transform, and load (ETL) layer is generated to extract item data from user data, transform the extracted data for storing in the database structure, and load the transformed extracted data into the database structure.

Abstract: Aspects of the present disclosure describe methods and apparatuses that hide latency during an interaction between an attacking client device platform and a defending client device platform in a multiplayer game played over a network. The attacking client device platform predicts a successful attack will be made and delivers a hit event to the defending client device platform. In order to provide additional time to wait for a hit reply from the defending client device platform the attacking client device platform initiates an altered animation mode that lengthens the run-time of the animation. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: Systems, methods, and other embodiments associated with and\ adaptive data model and warehouse palette are provided. In one embodiment, a method includes providing a user interface for collecting item definition attributes from a user. A database structure is generated to store item data according to collected the item definition attributes. An extract, transform, and load (ETL) layer is generated to extract item data from user data, transform the extracted data for storing in the database structure, and load the transformed extracted data into the database structure.