Patents by Inventor Jason Mehigan

Jason Mehigan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230054430
    Abstract: According to an embodiment, an apparatus for a plasma processing system is provided. The apparatus includes an interface, a radiating structure, and conductive offsets. The interface includes a first conductive plate couplable to an RF source, a second conductive plate disposed between the RF source and the first conductive plate, and conductive concentric ring structures disposed between the second conductive plate and a substrate holder. The conductive offsets are arranged to couple the conductive concentric ring structures to the radiating structure.
    Type: Application
    Filed: May 23, 2022
    Publication date: February 23, 2023
    Inventors: Barton Lane, Yohei Yamazawa, Jason Mehigan, Merritt Funk
  • Patent number: 11302588
    Abstract: A method is provided for area-selective deposition on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting one or more film-forming modules, one or more etching modules, and one or more transfer modules. A workpiece having a target surface of a first material and a non-target surface of a second material different than the first material is received into the common manufacturing platform. An additive material is deposited on the workpiece with selectivity that results in the additive material forming on the target surface at a higher deposition rate than on the non-target surface, followed by etching to expose the non-target surface. The integrated sequence of processing steps is executed within the common manufacturing platform without leaving the controlled environment and the transfer modules are used to transfer the workpiece between the processing modules while maintaining the workpiece within the controlled environment.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: April 12, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Robert Clark, Kandabara Tapily, Jason Mehigan
  • Patent number: 11152268
    Abstract: A method is provided for area-selective deposition on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting film-forming modules, etching modules, and transfer modules. A workpiece having a target surface of a first material an non-target surface of a second material different than the first material is received into the platform. An additive material is selectively deposited on the workpiece with the additive material forming on the target surface at a higher deposition rate than on the non-target surface, followed by etching to expose the non-target surface. The integrated sequence of processing steps is executed within the platform without leaving the controlled environment and the transfer modules are used to transfer the workpiece between the processing modules while maintaining the workpiece within the controlled environment.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: October 19, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Robert Clark, Kandabara Tapily, Jason Mehigan
  • Publication number: 20190295845
    Abstract: A method is provided for area-selective deposition on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting one or more film-forming modules, one or more etching modules, and one or more transfer modules. A workpiece having a target surface of a first material and a non-target surface of a second material different than the first material is received into the common manufacturing platform. An additive material is deposited on the workpiece with selectivity that results in the additive material forming on the target surface at a higher deposition rate than on the non-target surface, followed by etching to expose the non-target surface. The integrated sequence of processing steps is executed within the common manufacturing platform without leaving the controlled environment and the transfer modules are used to transfer the workpiece between the processing modules while maintaining the workpiece within the controlled environment.
    Type: Application
    Filed: March 18, 2019
    Publication date: September 26, 2019
    Inventors: Robert Clark, Kandabara Tapily, Jason Mehigan
  • Publication number: 20190295903
    Abstract: A method is provided for area-selective deposition on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting film-forming modules, etching modules, and transfer modules. A workpiece having a target surface of a first material an non-target surface of a second material different than the first material is received into the platform. An additive material is selectively deposited on the workpiece with the additive material forming on the target surface at a higher deposition rate than on the non-target surface, followed by etching to expose the non-target surface. The integrated sequence of processing steps is executed within the platform without leaving the controlled environment and the transfer modules are used to transfer the workpiece between the processing modules while maintaining the workpiece within the controlled environment.
    Type: Application
    Filed: March 18, 2019
    Publication date: September 26, 2019
    Inventors: Robert Clark, Kandabara Tapily, Jason Mehigan
  • Publication number: 20050208732
    Abstract: A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate—slower than that of other major crystallographic planes of the semiconductor material. The trench is etched into the semiconductor wafer. The trench has substantially vertical trench-sidewalls near the top surface, the vertical trench-sidewalls near the top surface containing crystallographic plane that oxidizes at a rate comparable to that of the top surface. An insulating layer is grown on the top surface and on the trench-sidewalls and on corners where sidewall surfaces approach the top surface, the insulating layer at the corners being substantially thicker than at the sidewall adjacent to the corners. The difference in the oxide thickness is due to the faster oxidizing planes exposed at the corners. Finally, the trench is filled with a dielectric material.
    Type: Application
    Filed: June 1, 2005
    Publication date: September 22, 2005
    Inventors: Zhihao Chen, Freidoon Mehrad, Brian Kirkpatrick, Jeff White, Edmund Russell, Jon Holt, Jason Mehigan
  • Publication number: 20050062127
    Abstract: A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate—slower than that of other major crystallographic planes of the semiconductor material. The trench is etched into the semiconductor wafer. The trench has substantially vertical trench-sidewalls near the top surface, the vertical trench-sidewalls near the top surface containing crystallographic plane that oxidizes at a rate comparable to that of the top surface. An insulating layer is grown on the top surface and on the trench-sidewalls and on corners where sidewall surfaces approach the top surface, the insulating layer at the corners being substantially thicker than at the sidewall adjacent to the corners. The difference in the oxide thickness is due to the faster oxidizing planes exposed at the corners. Finally, the trench is filled with a dielectric material.
    Type: Application
    Filed: October 23, 2003
    Publication date: March 24, 2005
    Inventors: Zhihao Chen, Freidoon Mehrad, Brian Kirkpatrick, Jeff White, Edmund Russell, Jon Holt, Jason Mehigan