Abstract: This invention is a video line encapsulation protocol which allows multiple low definition video streams to be combined into a single super frame of high definition video data. Each super frame is formed of individual lines from plural lower definition video input signals. The high definition video frames include meta data in each line identifying the video input source, line and frame. This meta data enables the super frames to be separated into their component input signals within a video processing digital signal processor.

Abstract: A method for controlling a network capable AV switching device 32 using a Zero Configuration Network protocol is claimed. The method uses a user created configuration data table 51 to create a plurality of virtual channels or devices 36 representing desired output states of the AV switching device 32. These virtual channels 36 are published to the network via a Zero Configuration Network protocol, such as Bonjour or UPnP. Each of these virtual channels 36 has a corresponding switching command list 54 for the AV switching device 32 that will be automatically activated when a connection to that virtual channel 36 is made. This allows the user to efficiently and simply control the operation of the AV switching device 32 through a single selection of one of the virtual channels 36.

Abstract: This invention is a video line encapsulation protocol which allows multiple low definition video streams to be combined into a single super frame of high definition video data. Each super frame is formed of individual lines from plural lower definition video input signals. The high definition video frames include meta data in each line identifying the video input source, line and frame. This meta data enables the super frames to be separated into their component input signals within a video processing digital signal processor.

Abstract: A system to reduce noise includes a noise measurement device that provides a measure of noise associated with a digital input video signal. A noise reduction filter provides a noise-reduced digital output video signal corresponding to the luma and chroma of the digital input video signal. The noise reduction filter has a parameter that varies on a pixel basis for the component of the digital input video signal as a function of the measure of noise. The range and sensitivity of the noise reduction can be user programmable.

Abstract: A video decoder (14). The decoder comprises an interface (30) for receiving a set of an integer number S of analog input signals at a same time. The decoder also comprises circuitry for processing the S analog input signals, and that circuitry comprises an integer number N of analog-to-digital converters (38x) for producing a set of the integer number S of digital signals. Each digital signal in the set of S of digital signals corresponds to a respective different one of the S analog input signal, and N is less than S. The decoder also comprises output circuitry (40x, 42x), coupled to the circuitry for processing, for providing each digital signal in the set of S of digital signals to a different respective output conductor.

Abstract: Systems and method are provided for luma-chroma separation. A demodulator system demodulates a composite video signal to produce at least two baseband chroma signals. A given baseband chroma signal contains chroma information for one of a plurality of video frames comprising the composite signal. A three-dimensional (3-D) comb filter removes luma information from a given baseband chroma signal by combining sets of at least two baseband chroma signals to form a 3-D filtered baseband signal.

Abstract: A video decoder (52, 152) including a digital-control oscillator (DCO) (60, 160) is disclosed. The DCO (60, 160) includes a first flying-adder frequency synthesis circuit (74S) that measures an input signal frequency, such as the horizontal sync frequency of an input video signal. A frequency control word (FREQ) is generated in response to this input signal frequency, and is applied to a second flying-adder frequency synthesis circuit (74), which in turn selects the appropriate phases for leading and trailing edges of the output clock signal (PIX_CLK). Phase tuning of the output clock signal (PIX_CLK) can be effected by using an alternate flying-adder frequency synthesis circuit (74?) architecture, in combination with a phase signal (PH) generated by a digital controller (61).

Abstract: Systems and method are provided for luma-chroma separation. A demodulator system demodulates a composite video signal to produce at least two baseband chroma signals. A given baseband chroma signal contains chroma information for one of a plurality of video frames comprising the composite signal. A three-dimensional (3-D) comb filter removes luma information from a given baseband chroma signal by combining sets of at least two baseband chroma signals to form a 3-D filtered baseband signal.

Abstract: A system to reduce noise includes a noise measurement device that provides a measure of noise associated with a digital input video signal. A noise reduction filter provides a noise-reduced digital output video signal corresponding to the luma and chroma of the digital input video signal. The noise reduction filter has a parameter that varies on a pixel basis for the component of the digital input video signal as a function of the measure of noise. The range and sensitivity of the noise reduction can be user programmable.

Abstract: A method for optimizing a digital filter that produces an output signal from samples of an input signal is configured with filter coefficients that are selected by a prescribed filter coefficient search. The filter coefficient search uses a pre-scaling constant or an additive constant with the filter coefficients and canonical signed digits to reduce filter cost or filter execution time. The coefficient search includes a precision for the filter coefficients and an allowable number of nonzero digits for each coefficient to produce a filter coefficient set with a reduced overall number of nonzero digits. The resulting filter can generally be implemented with substantially less integrated circuit die area than that obtainable with previous design approaches.

Abstract: A video decoder (14). The decoder comprises an interface (30) for receiving a set of an integer number S of analog input signals at a same time. The decoder also comprises circuitry for processing the S analog input signals, and that circuitry comprises an integer number N of analog-to-digital converters (38x) for producing a set of the integer number S of digital signals. Each digital signal in the set of S of digital signals corresponds to a respective different one of the S analog input signal, and N is less than S. The decoder also comprises output circuitry (40x, 42x), coupled to the circuitry for processing, for providing each digital signal in the set of S of digital signals to a different respective output conductor.

Abstract: A clamping circuit disclosed herein has two modes of operation which include both a bottom level and mid-level clamping mode for clamping automatically onto the sync tip of a video signal and customizably clamping onto the front porch, back porch/pedestal or anywhere within the signal. The clamping circuit (400) includes a clamping capacitor (404) that couples to an automatic clamping circuit portion (405) to automatically clamp the synchronization pulse of the video input signal to a first predetermined reference voltage (Vref1) of a first clamping pulse signal during an automatic clamping mode of operation. The automatic clamping portion (405) connects to the customizable clamping circuit portion (411) to clamp any portion of the video input signal to a second predetermined reference voltage (Vref2) of a second clamping pulse signal during a customizable clamping mode of operation. A buffer (416) connects between the customizable clamping circuit portion and the output node of the clamping circuit.

Abstract: A video decoder (52, 152) including a digital-control oscillator (DCO) (60, 160) is disclosed. The DCO (60, 160) includes a first flying-adder frequency synthesis circuit (74S) that measures an input signal frequency, such as the horizontal sync frequency of an input video signal. A frequency control word (FREQ) is generated in response to this input signal frequency, and is applied to a second flying-adder frequency synthesis circuit (74), which in turn selects the appropriate phases for leading and trailing edges of the output clock signal (PIX_CLK). Phase tuning of the output clock signal (PIX_CLK) can be effected by using an alternate flying-adder frequency synthesis circuit (74?) architecture, in combination with a phase signal (PH) generated by a digital controller (61).

Abstract: A method for identifying format of a video signal including a raster-synchronizing signal having a timing signal spanning a synch interval and a synch-follower signal level adjacent the synch interval, and a color-related signal, includes the steps: (a) ascertaining (1) first signal level of the color-related signal during the synch interval; (2) synch difference between level of the raster-synchronizing signal during the synch interval and the synch-follower level; and (3) peak excursion for the color-related signal; (b) in any order: (1) if first signal level is greater than a first value, set a first factor at one, else zero; (2) if synch difference is greater than a second value, set a second factor at one, else zero; and (3) if peak excursion is greater than a third value, set a third factor at zero, else one; and (c) employing the factors to identify the format according to predetermined relationships.

Abstract: A method for generating a representation of a particular signal among video signals representing a display, the signals including a first component having a first bandwidth and a second component having a smaller second bandwidth, includes the steps of: (a) measuring first samples of the first component outside the second bandwidth for an interval in each signal; (b)measuring second samples of the second component inside the second bandwidth for the interval; (c) establishing factors based upon first samples; (d) establishing filter modes based upon second samples; (e) establishing a correlation between factors and filter modes; (f) filtering the signals using a selected filter mode; (g) identifying a selected factor according to the correlation for the selected filter mode; (h) employing the selected factor for weighted mixing of the samples to generate the representation for the time interval; and (g) repeating steps (a) through (h) until the representation is completed.

Abstract: The present invention discloses a horizontal sync detector circuit (10) comprising a filter portion (12), an equilibrium accumulator portion (14) coupled to the filter portion (12), a horizontal sync detector portion (16) coupled to the filter portion (12) and to the equilibrium accumulator portion (14), and an output logic portion (18) coupled to the horizontal sync detector portion (16), the output logic portion (18) adapted to produce a phase error (116) based on a combination of a coarse phase error (108) and a fine phase error (112).

Abstract: A clamping circuit disclosed herein has two modes of operation which include both a bottom level and mid-level clamping mode for clamping automatically onto the sync tip of a video signal and customizably clamping onto the front porch, back porch/pedestal or anywhere within the signal. The clamping circuit (400) includes a clamping capacitor (404) that couples to an automatic clamping circuit portion (405) to automatically clamp the synchronization pulse of the video input signal to a first predetermined reference voltage (Vref1) of a first clamping pulse signal during an automatic clamping mode of operation. The automatic clamping portion (405) connects to the customizable clamping circuit portion (411) to clamp any portion of the video input signal to a second predetermined reference voltage (Vref2) of a second clamping pulse signal during a customizable clamping mode of operation. A buffer (416) connects between the customizable clamping circuit portion and the output node of the clamping circuit.