Patents by Inventor Jason Molgaard

Jason Molgaard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260178477
    Abstract: This application is directed to data buffering in a computational storage device (e.g., a memory device having data processing capability). A memory device includes one or more processors, a volatile memory, and a non-volatile memory storing a data set. A portion of the volatile memory is allocated to facilitating data processing, and further includes a buffer having a buffer size smaller than a data size of the data set. The memory device loads a subset of the data set from the non-volatile memory to the buffer, and identifies a first data portion having a predefined portion size. In accordance with a determination that the first data portion has been processed, the memory device loads a next data portion of the data set from the non-volatile memory to the buffer in place of a subset of the first data portion (e.g., less than all or all of the first data portion).
    Type: Application
    Filed: December 19, 2024
    Publication date: June 25, 2026
    Inventors: Steven WILLIAMS, Jason MOLGAARD
  • Publication number: 20260161541
    Abstract: This application is directed to a memory device including a non-volatile memory for storing user data, a first controller, and a companion compute component. The first controller is coupled to the non-volatile memory, and configured to receive a memory access request and access the non-volatile memory in response to the memory access request. The companion compute component is coupled to the first controller via a companion link, and the companion compute component and the first controller are distinct from one another. The companion compute component is configured to access the non-volatile memory storing the user data via the first controller and the companion link and process the user data internally in the memory device. In some embodiments, the first controller includes a host interface configured to enable data communication with a host device and a dedicated companion interface configured to enable data communication with the companion compute component.
    Type: Application
    Filed: December 11, 2024
    Publication date: June 11, 2026
    Inventors: Jason MOLGAARD, Vladimir ALVES, Steven WILLIAMS
  • Patent number: 12578875
    Abstract: This application is directed to preparing and processing data locally in a memory system that includes a data processor, a memory controller, and a non-volatile memory (e.g., NAND flash memory). The memory system obtaining a request for processing first data. A modified form of the first data has been stored as second data in the non-volatile memory. The memory system identifies the second data stored in the non-volatile memory, and extracts the second data from the non-volatile memory. The second data is processed by the memory controller of the memory system to recover the first data, which are further provided to the data processor for processing locally within the memory system. In some embodiments, the memory controller temporarily stores the second data in a first memory and the recovered first data in a second memory from which the data processor extracts the recovered first data for further local on-memory processing.
    Type: Grant
    Filed: July 30, 2024
    Date of Patent: March 17, 2026
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventors: Vincent Lazo, Guangming Lu, Jason Molgaard
  • Publication number: 20260037324
    Abstract: This application is directed to resource management in a storage system that includes a non-volatile memory and a collection of resources having one or more processing cores. The storage system allocates a first subset of resources to process queues of I/O access operations requested by a host device. The first subset of resources includes a storage controller corresponding to a subset of processing cores. The storage system obtains a first request for adjusting resource allocation of the storage device, and the first request includes a target performance requirement for processing the queues of I/O access operations. The storage system determines that the target performance requirement can be satisfied by allocation of at least a target subset of resources. In response to the first request and based on the target subset of resources, a second subset of resources is allocated for processing the one or more queues of I/O access operations.
    Type: Application
    Filed: August 5, 2024
    Publication date: February 5, 2026
    Inventors: Vinit VYAS, Hermes Alexandre ALCANTARA SILVA COSTA, Vladimir ALVES, Jason MOLGAARD
  • Publication number: 20260037141
    Abstract: This application is directed to preparing and processing data locally in a memory system that includes a data processor, a memory controller, and a non-volatile memory (e.g., NAND flash memory). The memory system obtaining a request for processing first data. A modified form of the first data has been stored as second data in the non-volatile memory. The memory system identifies the second data stored in the non-volatile memory, and extracts the second data from the non-volatile memory. The second data is processed by the memory controller of the memory system to recover the first data, which are further provided to the data processor for processing locally within the memory system. In some embodiments, the memory controller temporarily stores the second data in a first memory and the recovered first data in a second memory from which the data processor extracts the recovered first data for further local on-memory processing.
    Type: Application
    Filed: July 30, 2024
    Publication date: February 5, 2026
    Inventors: Vincent LAZO, Guangming LU, Jason MOLGAARD
  • Publication number: 20100011172
    Abstract: A microcontroller system includes at least one processor and at least one storage unit for storing data received from or to be sent to the processor. At least two read clients are provided in the processor for retrieving data from the storage unit, and at least one write client is provided in the processor for writing data in the storage unit. The system further includes a memory device provided in the storage unit for storing data, and an arbitration device provided in the storage unit for enabling access to the memory device by the read and the write client. The read clients each have a dedicated read address line connected to the arbitration device for sending a read address of read data to be retrieved from the memory device, and a shared read data bus connected to the memory device for receiving the read data from the read address.
    Type: Application
    Filed: July 9, 2008
    Publication date: January 14, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Jason Molgaard, Michael James, Bradford Lincoln
  • Publication number: 20090292885
    Abstract: Apparatus for controlling atomic access to a memory includes an access request evaluator for receiving an atomic access request to an address in the memory from a client and determining whether to allow atomic access to the requested address. An access indicator indicates whether a select address is currently under atomic access in the memory, and an access release indicates whether the atomic access is completed at the select address. The access request evaluator enables the client atomic access to the requested address if the access indicator indicates that the requested address is currently not under atomic access.
    Type: Application
    Filed: May 22, 2008
    Publication date: November 26, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Jason Molgaard, Michael James, Bradford Lincoln
  • Publication number: 20080155296
    Abstract: Apparatus for controlling input clock signals to a microprocessor includes a clock generator for generating the input clock signals to the microprocessor, and a clock controller for producing a control signal for disabling the clock generator from outputting the input clock signals to the microprocessor for a predetermined time. The clock generator resumes outputting the input clock signals to the microprocessor after the predetermined time.
    Type: Application
    Filed: December 22, 2006
    Publication date: June 26, 2008
    Inventors: Michael James, Bradford C. Lincoln, Jason Molgaard