Patents by Inventor Jason Muhlestein

Jason Muhlestein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230208432
    Abstract: An apparatus, system, and method for digital-to-analog (converter) control are provided. A DAC includes a first resistor ladder including a plurality of first electrical taps into different portions of the first resistor ladder, first and second pass gate trees coupled to receive outputs from the first electrical taps, first and second buffers coupled to receive outputs from the first and second pass gate trees, respectively, a second resistor ladder coupled to receive and be biased by outputs of the first and second buffers, the second resistor ladder including a plurality of second electrical taps into different portions of the second resistor ladder, and third, fourth, and fifth pass gate trees coupled to receive outputs from the second electrical taps.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: Fabrice Paillet, Jason Muhlestein, James Keith Hodgson, SHIVADARSHAN BIDADI RAJEURS, George Matthew, Anand Ramasundar, Cary Renzema, Po-Cheng Chen, Sergio Carlo Rodriguez, Seng Rou Tey
  • Publication number: 20230205244
    Abstract: An apparatus, system, and method for digital voltage regulator (DVR) control are provided. A DVR includes comparators configured to determine whether VLOAD drops below a gradual non-linear control (NLC) undershoot threshold voltage, rises above or drops below a reference voltage, and rises above a gradual NLC overshoot threshold voltage, respectively, power gates (PGs) configured to adjust VOUT based on a provided PG code; and VR controller circuitry comprising synchronous LC circuitry configured to increase or decrease, by a first increment, the PG code responsive to the VLOAD dropping below the reference voltage and rising above the reference voltage, and asynchronous gradual NLC circuitry configured to increase or decrease, by a second increment greater than the first increment and less than half a maximum PG code value, the PG code responsive to the VLOAD dropping below the gradual NLC undershoot threshold voltage and rising above the gradual NLC overshoot threshold voltage.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: Anand Ramasundar, Cary Renzema, Fabrice Paillet, James Keith Hodgson, Po-Cheng Chen, Sergio Carlo Rodriguez, Harish K. Krishnamurthy, Jason Muhlestein