Abstract: A system for tolerating a single event fault in an electronic circuit is disclosed. The system includes a main processor that controls the operation of the system, a fault detection processor responsive to the main processor, and three or more programmable logic devices responsive to the fault detection processor. The three or more programmable logic devices periodically issue independent input signals to the fault detection processor for determination of one or more single event fault conditions.

Abstract: A distributed processing network is disclosed. The network includes at least one network switch, coupled to one or more end nodes, and adapted to simultaneously receive and route a plurality of data packets between the one or more end nodes. Within the network, the one or more end nodes are interconnected by one or more communication links adapted to provide a predetermined level of fault tolerant error detection and recovery.

Abstract: A reconfigurable computer includes a reconfigurable processing element configured to process raw payload data in accordance with a configuration that is applied to the reconfigurable processing element. The reconfigurable computer further includes a multi-port communication device comprising a first port at which at least a portion of the raw payload data is written to the multi-port communication device and a second port at which at least a portion raw payload data written to the multi-port communication device is read by the reconfigurable processing element. The reconfigurable computer further includes a controller coupled to the reconfigurable processing element. The controller applies the configuration to the reconfigurable processing element and wherein the controller performs at least one single event upset mitigation operation.