Abstract: A test structure used to determine reliability performance includes a patterned metallization structure having multiple interfaces, which provide stress risers. A dielectric material surrounds the metallization structure, where a mismatch in coefficients of thermal expansion (CTE) between the metallization structure and the surrounding dielectric material exist such that a thermal strain value is provided to cause failures under given stress conditions as a result of CTE mismatch to provide a yield indicative of reliability for a manufacturing design.

Abstract: A test structure used to determine reliability performance includes a patterned metallization structure having multiple interfaces, which provide stress risers. A dielectric material surrounds the metallization structure, where a mismatch in coefficients of thermal expansion (CTE) between the metallization structure and the surrounding dielectric material exist such that a thermal strain value is provided to cause failures under given stress conditions as a result of CTE mismatch to provide a yield indicative of reliability for a manufacturing design.

Abstract: The present invention provides a micro-electro-mechanical-system (MEMS) temperature sensor that employs a suspended spiral comprising a material with a positive coefficient of thermal expansion. The thermal expansion of the suspended spiral is guided to by a set of guideposts to provide a linear movement of the free end of the suspended spiral, which is converted to an electrical signal by a set of conductive rotor azimuthal fins that are interdigitated with a set of conductive stator azimuthal fins by measuring the amount of capacitive coupling therebetween. Real time temperature may thus be measured through the in-situ measurement of the capacitive coupling. Optionally, the MEMS temperature sensor may have a ratchet and a pawl to enable ex-situ measurement.

Abstract: The present invention provides a micro-electro-mechanical-system (MEMS) temperature sensor that employs a suspended spiral comprising a material with a positive coefficient of thermal expansion. The thermal expansion of the suspended spiral is guided to by a set of guideposts to provide a linear movement of the free end of the suspended spiral, which is converted to an electrical signal by a set of conductive rotor azimuthal fins that are interdigitated with a set of conductive stator azimuthal fins by measuring the amount of capacitive coupling therebetween. Real time temperature may thus be measured through the in-situ measurement of the capacitive coupling. Optionally, the MEMS temperature sensor may have a ratchet and a pawl to enable ex-situ measurement.

Abstract: An interconnect structure which includes a metal-containing cap located atop each conductive feature that is present within a dielectric material is provided in which a surface region of the metal-containing cap is oxidized prior to the subsequent deposition of any other dielectric material thereon. Moreover, metal particles that are located on the surface of the dielectric material between the conductive features are also oxidized at the same time as the surface region of the metal-containing cap. This provides a structure having a reduced leakage current. In accordance with the present invention, the oxidation step is performed after electroless plating of the metal-containing cap and prior to the deposition of a dielectric capping layer or an overlying interlayer or intralevel dielectric material.

Abstract: A method of fabricating a device includes depositing a electromigration (EM) resistive material in an etched trench formed in a substrate and a wiring layer. The EM resistive material is formed in electrical contact with an underlying diffusion barrier layer and wiring layer. The method further includes forming a via structure in electrical contact with the EM resistive material and the wiring layer. The method results in a structure which prevents an open circuit.

Abstract: A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate.

Abstract: An interconnect structure which includes a metal-containing cap located atop each conductive feature that is present within a dielectric material is provided in which a surface region of the metal-containing cap is oxidized prior to the subsequent deposition of any other dielectric material thereon. Moreover, metal particles that are located on the surface of the dielectric material between the conductive features are also oxidized at the same time as the surface region of the metal-containing cap. This provides a structure having a reduced leakage current. In accordance with the present invention, the oxidation step is performed after electroless plating of the metal-containing cap and prior to the deposition of a dielectric capping layer or an overlying interlayer or intralevel dielectric material.

Abstract: A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (?m).

Abstract: An interconnect structure which includes a metal-containing cap located atop each conductive feature that is present within a dielectric material is provided in which a surface region of the metal-containing cap is oxidized prior to the subsequent deposition of any other dielectric material thereon. Moreover, metal particles that are located on the surface of the dielectric material between the conductive features are also oxidized at the same time as the surface region of the metal-containing cap. This provides a structure having a reduced leakage current. In accordance with the present invention, the oxidation step is performed after electroless plating of the metal-containing cap and prior to the deposition of a dielectric capping layer or an overlying interlayer or intralevel dielectric material.

Abstract: A method of fabricating a device includes depositing a electromigration (EM) resistive material in an etched trench formed in a substrate and a wiring layer. The EM resistive material is formed in electrical contact with an underlying diffusion barrier layer and wiring layer. The method further includes forming a via structure in electrical contact with the EM resistive material and the wiring layer. The method results in a structure which prevents an open circuit.

Abstract: A method of fabricating a device includes depositing a electromigration (EM) resistive material in an etched trench formed in a substrate and a wiring layer. The EM resistive material is formed in electrical contact with an underlying diffusion barrier layer and wiring layer. The method further includes forming a via structure in electrical contact with the EM resistive material and the wiring layer. The method results in a structure which prevents an open circuit.

Abstract: An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a layer that includes a first and second wire which do not physically touch each other. The first and second wires are adapted to be at an elevated temperature due to Joule heating in relation to electrical current density in the first and second wires. The first wire is electrically and thermally coupled to the second wire by an electrically and thermally conductive structure that exists outside of the layer. The width of the second wire is tailored so as to limit a temperature gradient in the first wire to be below a threshold value that is predetermined to be sufficiently small so as to substantially mitigate adverse effects of electromigration in the first wire.

Abstract: Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines are formed on a wafer each of which includes multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line geometry adjustment is determined based on the electrical resistances of all the sections. The first line geometry adjustment represents an effective reduction of cross-section size of the lines due to grain boundary electrical resistance. A second plurality of lines of same length and thickness can be formed on the same wafer. Then, second and third line geometry adjustments are determined based on the electrical resistances of these lines measured at different temperatures. The second and third line geometry adjustments represent an effective reduction of cross-section size of the lines due to grain boundary electrical resistance and line surface roughness.

Abstract: A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate.

Abstract: Disclosed are embodiments of a device and method of forming the device that utilize metal ion migration under controllable conditions. The device embodiments comprise two metal electrodes separated by one or more different dielectric materials. One electrode is sealed from the dielectric material, the other is not. The device is adapted to allow controlled migration of embedded metal ions from the unsealed electrode into dielectric material to form a conductive path under field between the electrodes and, thereby, to decrease the resistance of the dielectric material. Reversing the field causes the metal ions to reverse their migration, to break the conductive metallic path between the electrodes and, thereby, to increase the resistance of the dielectric material. Thus, the device can comprise a simple switch or programmable resistor.

Abstract: A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (?m).

Abstract: Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines can be formed on a wafer each of which comprises multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line geometry adjustment is determined based on the electrical resistances of all the sections of all the lines. The first line geometry adjustment represents an effective reduction of cross-section size of the lines due to grain boundary electrical resistance. A second plurality of lines of same length and thickness can be formed on the same wafer. Then, second and third line geometry adjustments can be determined based on the electrical resistances of these lines measured at different temperatures. The second and third line geometry adjustments represent an effective reduction of cross-section size of the lines due to grain boundary electrical resistance and line surface roughness.

Abstract: A method and system for forming a semiconductor device having superior ESD protection characteristics. A resistive material layer is disposed within a contact hole on at least one of the contact stud upper and lower surface. In preferred embodiments, the integral resistor has a resistance value of between about one Ohm and about ten Ohms, or between 10 and 100 Ohms. Embodiments of the resistive layer include sputtered silicon material, a tunnel oxide, a tunnel nitride, a silicon-implanted oxide, a silicon-implanted nitride, or an amorphous polysilicon. Embodiments of the invention include SRAMs, bipolar transistors, SOI lateral diodes, MOSFETs and SiGe Transistors.

Abstract: An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a layer that includes a first and second wire which do not physically touch each other. The first and second wires are adapted to be at an elevated temperature due to Joule heating in relation to electrical current density in the first and second wires. The first wire is electrically and thermally coupled to the second wire by an electrically and thermally conductive structure that exists outside of the layer. The width of the second wire is tailored so as to limit a temperature gradient in the first wire to be below a threshold value that is predetermined to be sufficiently small so as to substantially mitigate adverse effects of electromigration in the first wire.