Patents by Inventor Jason P. Jaehnig

Jason P. Jaehnig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7859270
    Abstract: A passive CMOS differential mixer circuit with a mismatch correction circuit for balancing the electrical characteristics of the two output paths. Once the output paths of the differential circuit are balanced, or matched as closely as possible, second order intermodulation product generation can be inhibited or at least reduced to acceptable levels. The mismatch correction circuit receives a digital offset signal, and generates one or more voltage signals to be selectively applied to the signal paths of the passive differential mixer circuit. The voltage signals can be adjusted back gate bias voltages applied to the bulk terminals of selected transistors to adjust their threshold voltages, or the voltage signals can be adjusted common mode voltages applied directly to a selected signal path. Since the differential mixer circuit is passive, no DC current contribution to noise is generated.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: December 28, 2010
    Assignee: Icera Canada ULC
    Inventors: Sherif H. K. Embabi, Alan R. Holden, Jason P. Jaehnig, Abdellatif Bellaouar
  • Publication number: 20090261887
    Abstract: A passive CMOS differential mixer circuit with a mismatch correction circuit for balancing the electrical characteristics of the two output paths. Once the output paths of the differential circuit are balanced, or matched as closely as possible, second order intermodulation product generation can be inhibited or at least reduced to acceptable levels. The mismatch correction circuit receives a digital offset signal, and generates one or more voltage signals to be selectively applied to the signal paths of the passive differential mixer circuit. The voltage signals can be adjusted back gate bias voltages applied to the bulk terminals of selected transistors to adjust their threshold voltages, or the voltage signals can be adjusted common mode voltages applied directly to a selected signal path. Since the differential mixer circuit is passive, no DC current contribution to noise is generated.
    Type: Application
    Filed: June 29, 2009
    Publication date: October 22, 2009
    Inventors: Sherif H. K. Embabi, Alan R. Holden, Jason P. Jaehnig, Abdellatif Bellaouar
  • Patent number: 7554380
    Abstract: A passive CMOS differential mixer circuit with a mismatch correction circuit for balancing the electrical characteristics of the two output paths. Once the output paths of the differential circuit are balanced, or matched as closely as possible, second order intermodulation product generation can be inhibited or at least reduced to acceptable levels. The mismatch correction circuit receives a digital offset signal, and generates one or more voltage signals to be selectively applied to the signal paths of the passive differential mixer circuit. The voltage signals can be adjusted back gate bias voltages applied to the bulk terminals of selected transistors to adjust their threshold voltages, or the voltage signals can be adjusted common mode voltages applied directly to a selected signal path. Since the differential mixer circuit is passive, no DC current contribution to noise is generated.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: June 30, 2009
    Assignee: Icera Canada ULC
    Inventors: Sherif H. K. Embabi, Alan R. Holden, Jason P. Jaehnig, Abdellatif Bellaouar