Abstract: Systems, methods, and computer readable media to manage power for a graphics processor are described. When the power management component determines the graphics processor is idle when processing a current frame by the graphics processor, the power management component predicts an idle period for the graphics processor based on the work history. The power management component obtains a first latency value indicative of a power on time period and a second latency value indicative of a power off time period for a graphics processor component, such as graphics processor hardware. The power management component provides power instructions to transition the graphics processor component to the power off state based on a determination that a combined latency value of the first latency value and the second latency value is less than the idle period.

Abstract: Systems, methods, and computer readable media to perform out-of-order command scheduling for a graphics processor are described. A graphics driver receives commands committed to a graphics processor for execution. The graphics driver queues a first command to a first graphics driver virtual channel that submits commands to the graphics processor for execution. The first command is associated with a first set of resources. The graphics driver determines whether a second set of resources associated with the second command depends on the first set of resources. The graphics driver queues the second command to the first graphics driver virtual channel based on a determination that the second set of resources depends on the first set of resources. The graphics driver queues the second command to a second virtual channel based on a determination that the second set of resources does not depend on the first set of resources.

Abstract: Systems, methods, and computer readable media to perform out-of-order command scheduling for a graphics processor are described. A graphics driver receives commands committed to a graphics processor for execution. The graphics driver queues a first command to a first graphics driver virtual channel that submits commands to the graphics processor for execution. The first command is associated with a first set of resources. The graphics driver determines whether a second set of resources associated with the second command depends on the first set of resources. The graphics driver queues the second command to the first graphics driver virtual channel based on a determination that the second set of resources depends on the first set of resources. The graphics driver queues the second command to a second virtual channel based on a determination that the second set of resources does not depend on the first set of resources.

Abstract: Systems, methods, and computer readable media to manage power for a graphics processor are described. When the power management component determines the graphics processor is idle when processing a current frame by the graphics processor, the power management component predicts an idle period for the graphics processor based on the work history. The power management component obtains a first latency value indicative of a power on time period and a second latency value indicative of a power off time period for a graphics processor component, such as graphics processor hardware. The power management component provides power instructions to transition the graphics processor component to the power off state based on a determination that a combined latency value of the first latency value and the second latency value is less than the idle period.

Abstract: Power management techniques include a graphics processing unit (GPU) in which the GPU determines whether it is operating outside an operational limit and, when the GPU is operating outside the operational limit, the GPU alters performance of an operation to be performed texture processor within the GPU to reduce complexity of the operation. Otherwise, the GPU may perform the texture processing operation at its default complexity. These techniques provide a degree of power control not available in other techniques.

Abstract: In one embodiment, a system controls a duty cycle of a processor (e.g. a graphics processing unit (GPU)) to manage power. The GPU may include a snoop indicator that may control whether or not the GPU captures and/or responds to communications from another processor (e.g. a central processing unit (CPU) that executes a driver associate with the GPU). A snooze indicator may control whether or not the GPU is automatically repowered at the start of the next frame, or is repowered only if the communication indicating additional work has been received. In an embodiment, the GPU mode controls discussed above may permit the GPU firmware executed with the GPU itself to control duty cycle power down, independent of the driver executing on the CPU.

Abstract: In one embodiment, a system includes a power management controller that controls a duty cycle of a processor to manage power. By frequently powering up and powering down the processor during a period of time, the power consumption of the processor may be controlled while providing the perception that the processor is continuously available. Before powering the processor up, the power management control may determine whether or not there is work for the processor to perform. If there is no work to perform, the power management control may delay powering the processor up until there is work to perform, saving additional power. This additional power savings may be tracked, and may serve as a “credit” for the processor when subsequently powered up again.

Abstract: Power management techniques are disclosed for a graphics processing unit (GPU) in which the GPU determines whether it is operating outside an operational limit and, when the GPU is operating outside the operational limit, the GPU alters performance of an operation to be performed texture processor within the GPU to reduce complexity of the operation. Otherwise, the GPU may perform the texture processing operation at its default complexity. These techniques provide a degree of power control not available in other techniques.

Abstract: In one embodiment, a system controls a duty cycle of a processor (e.g. a graphics processing unit (GPU)) to manage power. The GPU may include a snoop indicator that may control whether or not the GPU captures and/or responds to communications from another processor (e.g. a central processing unit (CPU) that executes a driver associate with the GPU). A snooze indicator may control whether or not the GPU is automatically repowered at the start of the next frame, or is repowered only if the communication indicating additional work has been received. In an embodiment, the GPU mode controls discussed above may permit the GPU firmware executed with the GPU itself to control duty cycle power down, independent of the driver executing on the CPU.

Abstract: In one embodiment, a system includes a power management controller that controls a duty cycle of a processor to manage power. By frequently powering up and powering down the processor during a period of time, the power consumption of the processor may be controlled while providing the perception that the processor is continuously available. Before powering the processor up, the power management control may determine whether or not there is work for the processor to perform. If there is no work to perform, the power management control may delay powering the processor up until there is work to perform, saving additional power. This additional power savings may be tracked, and may serve as a “credit” for the processor when subsequently powered up again.

Abstract: In an embodiment, a processor that includes multiple cores may implement a power/performance-efficient stop mechanism for power gating. One or more first cores of the multiple cores may have a higher latency stop than one or more second cores of the multiple cores. The power control mechanism may permit continued dispatching of work to the second cores until the first cores have stopped. The power control mechanism may prevent dispatch of additional work once the first cores have stopped, and may power gate the processing in response to the stopping of the second cores. Stopping a core may include one or more of: requesting a context switch from the core or preventing additional work from being dispatched to the core and permitting current work to complete normally. In an embodiment, the processor may be a graphics processing unit (GPU).

Abstract: In one embodiment, a system includes a power management controller that controls a duty cycle of a processor to manage power. By frequently powering up and powering down the processor during a period of time, the power consumption of the processor may be controlled while providing the perception that the processor is continuously available. Before powering the processor up, the power management control may determine whether or not there is work for the processor to perform. If there is no work to perform, the power management control may delay powering the processor up until there is work to perform, saving additional power. This additional power savings may be tracked, and may serve as a “credit” for the processor when subsequently powered up again.