Patents by Inventor Jason P. Ritter

Jason P. Ritter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10141274
    Abstract: A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: November 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Edward C. Cooney, III, Fen Chen, Jonathan M. Pratt, Jason P. Ritter, Patrick S. Spinney, Anna Tilley
  • Publication number: 20180053734
    Abstract: A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.
    Type: Application
    Filed: October 31, 2017
    Publication date: February 22, 2018
    Inventors: Edward C. Cooney, III, Fen Chen, Jonathan M. Pratt, Jason P. Ritter, Patrick S. Spinney, Anna Tilley
  • Patent number: 9893023
    Abstract: A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: February 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Edward C. Cooney, III, Fen Chen, Jonathan M. Pratt, Jason P. Ritter, Patrick S. Spinney, Anna Tilley
  • Publication number: 20170263574
    Abstract: A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.
    Type: Application
    Filed: May 26, 2017
    Publication date: September 14, 2017
    Inventors: Edward C. Cooney, III, Fen Chen, Jonathan M. Pratt, Jason P. Ritter, Patrick S. Spinney, Anna Tilley
  • Patent number: 9708508
    Abstract: A composition and a method for chemical mechanical polishing. The composition includes a surfactant anion an alkyl alcohol and a diluent. The composition further includes abrasive particles and an oxidizer. The method includes providing the composition on a surface to be polished and polishing the surface by contacting the surface with a polishing pad.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: July 18, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Graham M. Bates, Michael T. Brigham, Joseph K. Comeau, Jason P. Ritter, Matthew T. Tiersch, Eva A. Shah, Eric J. White
  • Patent number: 9711464
    Abstract: A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: July 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Edward C. Cooney, III, Fen Chen, Jonathan M. Pratt, Jason P. Ritter, Patrick S. Spinney, Anna Tilley
  • Publication number: 20170084552
    Abstract: A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 23, 2017
    Inventors: Edward C. Cooney, III, Fen Chen, Jonathan M. Pratt, Jason P. Ritter, Patrick S. Spinney, Anna Tilley
  • Publication number: 20150267084
    Abstract: A composition and a method for chemical mechanical polishing. The composition includes a surfactant anion an alkyl alcohol and a diluent. The composition further includes abrasive particles and an oxidizer. The method includes providing the composition on a surface to be polished and polishing the surface by contacting the surface with a polishing pad.
    Type: Application
    Filed: June 8, 2015
    Publication date: September 24, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Graham M. Bates, Michael T. Brigham, Joseph K. Comeau, Jason P. Ritter, Matthew T. Tiersch, Eva A. Shah, Eric J. White
  • Patent number: 9057004
    Abstract: A composition and a method for chemical mechanical polishing. The composition includes a surfactant anion an alkyl alcohol and a diluent. The composition further includes abrasive particles and an oxidizer. The method includes providing the composition on a surface to be polished and polishing the surface by contacting the surface with a polishing pad.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Graham M. Bates, Michael T. Brigham, Joseph K. Comeau, Jason P. Ritter, Matthew T. Tiersch, Eva A. Shah, Eric J. White
  • Patent number: 8734665
    Abstract: A composition and a method for chemical mechanical polishing. The composition includes a surfactant anion an alkyl alcohol, a controlled amount of chloride ion source and a diluent. The composition further includes abrasive particles and an oxidizer. The method includes providing the composition on a surface to be polished and polishing the surface by contacting the surface with a polishing pad.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventors: Graham M. Bates, Michael T. Brigham, Joseph K. Comeau, Jason P. Ritter, Eva A. Shah, Matthew T. Tiersch, Eric J. White
  • Publication number: 20130092651
    Abstract: A composition and a method for chemical mechanical polishing. The composition includes a surfactant anion an alkyl alcohol, a controlled amount of chloride ion source and a diluent. The composition further includes abrasive particles and an oxidizer. The method includes providing the composition on a surface to be polished and polishing the surface by contacting the surface with a polishing pad.
    Type: Application
    Filed: October 12, 2011
    Publication date: April 18, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Graham M. Bates, Michael T. Brigham, Joseph K. Comeau, Jason P. Ritter, Eva A. Shah, Matthew T. Tiersch, Eric J. White
  • Publication number: 20130078811
    Abstract: A composition and a method for chemical mechanical polishing. The composition includes a surfactant anion an alkyl alcohol and a diluent. The composition further includes abrasive particles and an oxidizer. The method includes providing the composition on a surface to be polished and polishing the surface by contacting the surface with a polishing pad.
    Type: Application
    Filed: September 23, 2011
    Publication date: March 28, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Graham M. Bates, Michael T. Brigham, Joseph K. Comeau, Jason P. Ritter, Matthew T. Tiersch, Eva A. Shah, Eric J. White
  • Patent number: 7572739
    Abstract: A semiconductor structure fabrication method for removing a tape physically attached to a device side of the semiconductor substrate by an adhesive layer of the tape, wherein the adhesive layer comprises an adhesive material. The method includes the step of submerging the tape in a liquid chemical comprising monoethanolamine or an alkanolamine for a pre-specified period of time sufficient to allow for a separation of the tape from the semiconductor substrate without damaging devices on the semiconductor substrate.
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: August 11, 2009
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Codding, Timothy C Krywanczyk, Steven G. Perrotte, Jason P. Ritter
  • Publication number: 20090064763
    Abstract: A test environment and an associated method of testing and analyzing a semiconductor package material containing a molding compound, for stability in a sustained oxygen environment. Test samples are exposed to a pressurized gas containing oxygen, under elevated temperature below the glass transition temperature of the molding compound. Control samples are exposed to a pressurized inert gas under similar or more severe conditions of gas pressure, temperature, and humidity. At least one characteristic common to the test samples and the control samples is measured. A determination is made as to whether there exists at least one significant difference between the at least one measured characteristic of the test samples and the control samples.
    Type: Application
    Filed: July 18, 2008
    Publication date: March 12, 2009
    Inventors: Joseph K. V. Comeau, Adele M. Mahoney, Jason P. Ritter, Gerald J. Scilla, Charles H. Wilson
  • Patent number: 7442552
    Abstract: A test environment and an associated method of testing and analyzing a semiconductor package material containing a molding compound, for stability in a sustained oxygen environment. Test samples are exposed to a pressurized gas containing oxygen, under elevated temperature below the glass transition temperature of the molding compound. Control samples are exposed to a pressurized inert gas under similar or more severe conditions of gas pressure, temperature, and humidity. At least one characteristic common to the test samples and the control samples is measured. A determination is made as to whether there exists at least one significant difference between the at least one measured characteristic of the test samples and the control samples.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: October 28, 2008
    Assignee: International Business Machines Corporation
    Inventors: Joseph K. V. Comeau, Adele M. Mahoney, Jason P. Ritter, Gerald J. Scilla, Charles H. Wilson
  • Patent number: 7300796
    Abstract: A test environment and an associated method of testing and analyzing a semiconductor package material containing a molding compound, for stability in a sustained oxygen environment. Test samples are exposed to a pressurized gas containing oxygen, under elevated temperature below the glass transition temperature of the molding compound. Control samples are exposed to a pressurized inert gas under similar or more severe conditions of gas pressure, temperature, and humidity. At least one characteristic common to the test samples and the control samples is measured. A determination is made as to whether there exists at least one significant difference between the at least one measured characteristic of the test samples and the control samples.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: November 27, 2007
    Assignee: International Business Machines Corporation
    Inventors: Joseph K. V. Comeau, Adele M. Mahoney, Jason P. Ritter, Gerald J. Scilla, Charles H. Wilson