Abstract: A soft-error resistant redundant latch including a first stage and second stage, each stage coupled to receive and to latch a binary signal in a latched state. Each stage is arranged to maintain the latched state at an intermediary node of the stage in response to a feedback path internal to the stage and in response to a stage output signal from the other stage. Each stage is arranged to generate a stage output signal in response to the latched state of the stage. The state of each stage is set to a first selected state by selectively coupling a stage set transistor between a first power rail and the intermediary node of the first stage in response to a set signal. The stage set transistor of the first stage and the stage set transistor of the second stage are complementary types.

Abstract: A soft-error resistant redundant latch including a first stage and second stage, each stage coupled to receive and to latch a binary signal in a latched state. Each stage is arranged to maintain the latched state at an intermediary node of the stage in response to a feedback path internal to the stage and in response to a stage output signal from the other stage. Each stage is arranged to generate a stage output signal in response to the latched state of the stage. The state of each stage is set to a first selected state by selectively coupling a stage set transistor between a first power rail and the intermediary node of the first stage in response to a set signal. The stage set transistor of the first stage and the stage set transistor of the second stage are complementary types.