Abstract: A system, e.g., a system on a chip (SoC) includes a first domain including a first processor configured to boot the system; a second domain including a processing subsystem having a second processor; and isolation circuitry between the first domain and the second domain During boot-up of the system, the first processor provides code to the second domain. When the code is executed by the second processor, it configures the processing subsystem as either a safety domain or as a general-purpose processing domain. The safety domain may an external safety domain or an internal safety domain.

Abstract: In an aspect an apparatus for geometric part searching is presented. An apparatus includes at least a processor and a memory communicatively connected to the at least a processor. At least a processor is configured to generate a search index as a function of a plurality of part specification files. At least a processor is configured to receive an input part specification file. At least a processor is configured to generate a query for an input part as a function of an input part specification file and a search index. A query is configured to output a comparison of an input part specification file to a part estimation specification file. At least a processor is configured to identify a matching part estimation file from a plurality of query results.

Abstract: A system on a chip (SoC) includes a first domain comprising a first processor configured to boot the SoC, and a first debug subsystem, a second domain comprising a second processor, the second domain configurable as either a safety domain or a general-purpose processing domain, and isolation circuitry between the first domain and the second domain. During boot-up of the SoC, the first processor provides code to the second domain which, when executed by the second processor, configures the second domain as either a safety domain or as a general-purpose processing domain.

Abstract: A system on a chip (SoC) includes a first domain comprising a first processor configured to boot the SoC, and a first debug subsystem, a second domain comprising a second processor, the second domain configurable as either a safety domain or a general-purpose processing domain, and isolation circuitry between the first domain and the second domain. During boot-up of the SoC, the first processor provides code to the second domain which, when executed by the second processor, configures the second domain as either a safety domain or as a general-purpose processing domain.

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to ferroelectric random access memory (FRAM) devices with an enhanced capacitor architecture. Other embodiments may be disclosed or claimed.

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to three-dimensional ferroelectric random access memory (3D FRAM) devices with a sense transistor coupled to a plurality of capacitors to (among other things) help improve signal levels and scaling. Other embodiments may be disclosed or claimed.

Abstract: A method of evaluating a language model using negative data may include accessing a first language model that is trained using a first training corpus, and accessing a second language model. The second language model may be configured to generate outputs that are less grammatical than outputs generated by the first language model. The method may also include training the second language model using a second training corpus, and generating output text from the second language model. The method may further include testing the first language model using the output text from the second language model.

Abstract: A memory device comprises a series of alternating plate lines and an insulating material over a substrate. Two or more ferroelectric capacitors are through the series of alternating plate lines and an insulating material such that a first one of the ferroelectric capacitors is coupled to a first one of the plate lines and a second one of the ferroelectric capacitors is coupled to a second one of the plate lines. A plurality of substantially parallel bitlines is along a first direction over the two or more ferroelectric capacitors. A plurality of substantially parallel bitlines is along a first direction over the two or more ferroelectric capacitors. A plurality of substantially parallel wordlines is along a second direction orthogonal to the first direction over the two or more ferroelectric capacitors. An access transistor is located over and controls the two or more ferroelectric capacitors, the access transistor incorporating a first one of the bitlines and a first one of the wordlines.

Abstract: Thin film transistors fabricated using a spacer as a fin are described. In an example, a method of forming a fin transistor structure includes patterning a plurality of backbone pillars on a semiconductor substrate. The method may then include conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate. A spacer etch of the spacer layer is then performed to leave a sidewall of the spacer layer on a backbone pillar to form a fin of the fin transistor structure.

Abstract: A method of evaluating a language model using negative data may include accessing a first language model that is trained using a first training corpus, and accessing a second language model. The second language model may be configured to generate outputs that are less grammatical than outputs generated by the first language model. The method may also include training the second language model using a second training corpus, and generating output text from the second language model. The method may further include testing the first language model using the output text from the second language model.

Abstract: A method of laser-assisted plasma etching with polarized light comprises providing a surface of a substrate that includes at least one surface region having trenches arranged in a unidirectional pattern along an x-direction or a y-direction of the surface, where each trench has a depth along a z-direction. The trenches extend substantially in parallel with each other and have a half-pitch of about 100 nm or less. The surface is exposed to a plasma and simultaneously illuminated with a pulsed laser beam having a predetermined polarization along the x-direction or the y-direction, and the trenches are etched.

Abstract: A method of laser-assisted plasma etching with polarized light comprises providing a surface of a substrate that includes at least one surface region having trenches arranged in a unidirectional pattern along an x-direction or a y-direction of the surface, where each trench has a depth along a z-direction. The trenches extend substantially in parallel with each other and have a half-pitch of about 100 nm or less. The surface is exposed to a plasma and simultaneously illuminated with a pulsed laser beam having a predetermined polarization along the x-direction or the y-direction, and the trenches are etched.

Abstract: A series of instructions from executable code are implemented on a processor core which in turn outputs event data. A watermark counter inputs event data and counts the number of events that occur within a time period defined by a start and stop signal. The watermark counter outputs a count value, corresponding to the number of events counted in the time period, across a connection to a monitoring computer.

Abstract: Provided are a method, system, and program for rendering a visualization of network devices in a computer user interface. A rendering is made of device representations of a plurality of devices in a network and of connection representations of connections between devices, wherein the connection representation between each pair of connected devices comprises a line extending between the two connected devices that forms approximately a ninety degree angle.