Abstract: Memory array circuits including word line circuits providing word line signal stability are disclosed. In a memory access operation, the states of word line signals on word lines in the memory rows of the memory array may be based on the states of word line latches during a first clock state of a latch clock signal. The word line latches receive address decode signals generated from a decoded memory address. An inverted delay clock circuit generates a clock pulse from the latch clock signal. The word line latches store the address decode signals during the clock pulse and generate word line signals based on the stored address decode signals. The memory address is received from an address bus. Pass-through address capture latches maximize time available to a decoder for decoding the memory address and word line latches reduce fluctuations in the address signal being propagated to the word line signals.

Abstract: Memory array circuits including word line circuits providing word line signal stability are disclosed. In a memory access operation, the states of word line signals on word lines in the memory rows of the memory array may be based on the states of word line latches during a first clock state of a latch clock signal. The word line latches receive address decode signals generated from a decoded memory address. An inverted delay clock circuit generates a clock pulse from the latch clock signal. The word line latches store the address decode signals during the clock pulse and generate word line signals based on the stored address decode signals. The memory address is received from an address bus. Pass-through address capture latches maximize time available to a decoder for decoding the memory address and word line latches reduce fluctuations in the address signal being propagated to the word line signals.

Abstract: Memory array circuitry includes a semiconductor substrate, a continuous diffusion in the semiconductor substrate, memory bit-cell circuitry, and support circuitry for the memory bit-cell circuitry. The continuous diffusion is a contiguous doped region of the semiconductor substrate. The memory bit-cell circuitry includes a bit-cell transistor formed on the continuous diffusion. The support circuitry includes a support transistor also formed on the continuous diffusion. By including both a bit-cell transistor and a support transistor on the same continuous diffusion, the necessary isolation between the bit-cell circuitry and the support circuitry may be reduced and the bit-cell transistor and the support transistor may have reduced length of diffusion (LOD) effects.

Abstract: A method and apparatus for reading bitcell data stored in a content addressable memory (CAM) includes controlling a first compare line of a first column of an array of bitcells to a first logic state while controlling a second compare line of the first column as well as first and second compare lines of each of the other columns of the array to a second logic state during a second mode of operation, in order to provide the bitcell data stored in at least one bitcell of the first column to a respective match line. The method also includes reading the bitcell data on the respective match line.

Abstract: In an array that qualifies each row according to a valid/invalid state, each row may each include valid-gated read circuitry to conditionally block a read wordline from toggling unless the row stores a data word that has a valid state or a read force signal is asserted. Furthermore, in a write operation, each row may have valid-gated write circuitry that conditionally blocks a write wordline from toggling unless input data to be written to the row has a valid state or a write force signal is asserted. Moreover, output latch clocking may be blocked from toggling unless a row to be read stores a data word that has a valid state or the read force signal is asserted, and input latch clocking may also be blocked unless the input data to be written has a valid state or the write force signal is asserted.

Abstract: Systems and methods for generating voltage level shifted self-clocked write assistance include a circuit with self-clocked true and complement data input signals in a first voltage domain. First and second full voltage level shifters are configured to generate voltage level shifted self-clocked intermediate true and complement signals in a second voltage domain, based on the self-clocked true and complement data input signals in the first voltage domain. Tristating logic including first and second complementary metal oxide semiconductor (CMOS) circuits are configured to generate voltage level shifted self-clocked tristated true and complement output signals used for providing write assistance for a memory array in the second voltage domain, based on the voltage level shifted self-clocked intermediate true and complements signals.

Abstract: Systems and methods for generating voltage level shifted self-clocked write assistance include a circuit with self-clocked true and complement data input signals in a first voltage domain. First and second full voltage level shifters are configured to generate voltage level shifted self-clocked intermediate true and complement signals in a second voltage domain, based on the self-clocked true and complement data input signals in the first voltage domain. Tristating logic including first and second complementary metal oxide semiconductor (CMOS) circuits are configured to generate voltage level shifted self-clocked tristated true and complement output signals used for providing write assistance for a memory array in the second voltage domain, based on the voltage level shifted self-clocked intermediate true and complements signals.

Abstract: A register file circuit according to some examples of the disclosure may include a memory cell, a header transistor circuit, and a driver circuit. The header transistor circuit may include one or more PFET headers in series with the PFETs of the memory cell with the gate of the PFET header for the row being written being controlled with a pulse write signal from the driver circuit. In some examples of the disclosure, the header transistor circuit may include an NFET pull-down inserted between a virtual-vdd and ground to discharge the virtual-vdd node reducing the contention during a write operation and a clamping NFET in parallel with the PFET header to clamp the virtual-vdd node to slightly below the threshold voltage of the pull-up PFET in the memory cell to ensure the pull-up PFET is barely off and prevent the virtual-vdd node from discharging all the way to ground.

Abstract: Static random access memory (SRAM) global bitline circuits for reducing glitches during read accesses, and related methods and systems are disclosed. A global bitline scheme in SRAM can reduce output load, reducing power consumption. In certain embodiments, SRAM includes an SRAM array. The SRAM includes a global bitline circuit for each SRAM array column. Each global bitline circuit includes memory access circuit that pre-charges local bitlines corresponding to bitcells in SRAM array. The data read from selected bitcell is read from its local bitline onto aggregated read bitline, an aggregation of local bitlines. The SRAM includes bitline evaluation circuit that sends data from aggregated read bitline onto global bitline. Instead of sending data based on rising transition of clock trigger, data is sent onto the global bitline based on falling transition of clock trigger. A global bitline scheme can be employed that reduces glitches and resulting increases in power consumption.

Abstract: Embodiments of a Content Addressable Memory (CAM) enabling high-speed search and invalidate operations and methods of operation thereof are disclosed. In one embodiment, the CAM includes a CAM cell array including a number of CAM cells and a valid bit cell configured to generate a match indicator, and blocking circuitry configured to block an output of the valid bit cell from altering the match indicator during an invalidate process of a search and invalidate operation. Preferably, the output of the valid bit cell is blocked from affecting the match indicator for the CAM cell array beginning at a start of the invalidate process and continuing until an end of the search and invalidate operation.

Abstract: Embodiments of a Content Addressable Memory (CAM) enabling high-speed search and invalidate operations and methods of operation thereof are disclosed. In one embodiment, the CAM includes a CAM cell array including a number of CAM cells and a valid bit cell configured to generate a match indicator, and blocking circuitry configured to block an output of the valid bit cell from altering the match indicator during an invalidate process of a search and invalidate operation. Preferably, the output of the valid bit cell is blocked from affecting the match indicator for the CAM cell array beginning at a start of the invalidate process and continuing until an end of the search and invalidate operation.

Abstract: Embodiments of a Content Addressable Memory (CAM) enabling high-speed search and invalidate operations and methods of operation thereof are disclosed. In one embodiment, the CAM includes a CAM cell array including a number of CAM cells and a valid bit cell configured to generate a match indicator, and blocking circuitry configured to block an output of the valid bit cell from altering the match indicator during an invalidate process of a search and invalidate operation. Preferably, the output of the valid bit cell is blocked from affecting the match indicator for the CAM cell array beginning at a start of the invalidate process and continuing until an end of the search and invalidate operation.

Abstract: Embodiments of a Content Addressable Memory (CAM) enabling high-speed search and invalidate operations and methods of operation thereof are disclosed. In one embodiment, the CAM includes a CAM cell array including a number of CAM cells and a valid bit cell configured to generate a match indicator, and blocking circuitry configured to block an output of the valid bit cell from altering the match indicator during an invalidate process of a search and invalidate operation. Preferably, the output of the valid bit cell is blocked from affecting the match indicator for the CAM cell array beginning at a start of the invalidate process and continuing until an end of the search and invalidate operation.

Abstract: Static-based comparators and methods for comparing data are disclosed. The static-based comparator is configured to selectively switch at least one comparator output in response to a comparison of corresponding data with compare data, and a validity indicator for the data. If the validity indicator indicates valid data, the static-based comparator switches to drive the comparator output indicating either a match or mismatch between corresponding compared data. If the validity indicator indicates invalid data, the static-based comparator provides a mismatch on the comparator output without switching the static-based comparator regardless of whether or not the data matches the compare data. In this manner, the static-based comparator does not dissipate power switching the comparator output for data marked invalid. The static-based comparator can be employed in content addressable memories (CAMs) for comparing one or more bits of tag data to corresponding bit(s) of compare data.

Abstract: A content addressable memory (CAM) is disclosed. The CAM has first and second CAM cells in which each adjacent CAM cell is rotated 180° relative to its neighbor, which provides a compact physical arrangement having overall matched CAM array cell and RAM array cell row heights. Further, an interleaved set scheme can be applied to the CAM cells to provide reduced routing of compare signals and reduced parasitic capacitance.

Abstract: Static-based comparators and methods for comparing data are disclosed. The static-based comparator is configured to selectively switch at least one comparator output in response to a comparison of corresponding data with compare data, and a validity indicator for the data. If the validity indicator indicates valid data, the static-based comparator switches to drive the comparator output indicating either a match or mismatch between corresponding compared data. If the validity indicator indicates invalid data, the static-based comparator provides a mismatch on the comparator output without switching the static-based comparator regardless of whether or not the data matches the compare data. In this manner, the static-based comparator does not dissipate power switching the comparator output for data marked invalid. The static-based comparator can be employed in content addressable memories (CAMs) for comparing one or more bits of tag data to corresponding bit(s) of compare data.

Abstract: A content addressable memory (CAM) is disclosed. The CAM has first and second CAM cells in which each adjacent CAM cell is rotated 180° relative to its neighbor, which provides a compact physical arrangement having overall matched CAM array cell and RAM array cell row heights. Further, an interleaved set scheme can be applied to the CAM cells to provide reduced routing of compare signals and reduced parasitic capacitance.