Patents by Inventor Jason Phillip Cain

Jason Phillip Cain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7460922
    Abstract: The disclosed embodiments reduce across-chip performance variation through non-contact electrical metrology. According to a feature is a process control system that includes a component that measures transistor electrical performance in a product wafer. Also included in the system is a mapping component that converts the transistor performance into exposure dose values and a process tool that communicates the exposure dose value to a scanner. The exposure dose value is fed back for optimization of future chip exposures. The disclosed embodiments directly optimize transistor performance, thus controlling an important parameter in many integrated circuits.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: December 2, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bhanwar Singh, Jason Phillip Cain, Harish Kumar Bolla, Iraj Emami
  • Patent number: 7373215
    Abstract: The claimed subject matter can provide a mechanism for ascertaining a variety of metrological data relating to one or more features (e.g., a transistor gate) of a chip/wafer. In addition, results of electrical testing on the chip/wafer can also be gathered and, together with the metrological data, input to a data store. From the information in the data store, a three-dimensional model for the feature(s) of the chip/wafer can be constructed and subjected to analysis, testing, and/or simulation. As well, the three-dimensional model can be optimized and an optimized three-dimensional model can be employed to affect process control in a feedback/forward manner, e.g., to apply optimizations to the next or the current wafer, respectively. Accordingly, the disclosed mechanisms may be used to optimize semiconductor performance, yield, or for research and development. In addition the three-dimensional model may be used in analysis, simulation, or debugging software.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: May 13, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jason Phillip Cain, Bhanwar Singh, Iraj Emami
  • Publication number: 20080058978
    Abstract: The claimed subject matter can provide a mechanism for ascertaining a variety of metrological data relating to one or more features (e.g., a transistor gate) of a chip/wafer. In addition, results of electrical testing on the chip/wafer can also be gathered and, together with the metrological data, input to a data store. From the information in the data store, a three-dimensional model for the feature(s) of the chip/wafer can be constructed and subjected to analysis, testing, and/or simulation. As well, the three-dimensional model can be optimized and an optimized three-dimensional model can be employed to affect process control in a feedback/forward manner, e.g., to apply optimizations to the next or the current wafer, respectively. Accordingly, the disclosed mechanisms may be used to optimize semiconductor performance, yield, or for research and development. In addition the three-dimensional model may be used in analysis, simulation, or debugging software.
    Type: Application
    Filed: August 31, 2006
    Publication date: March 6, 2008
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Jason Phillip Cain, Bhanwar Singh, Iraj Emami