Patents by Inventor Jason Pritchard
Jason Pritchard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230307854Abstract: A circuit board assembly may include a circuit board, a connector electrically and mechanically coupled to the circuit board and comprising at least one circuit board pin extending from the connector, each circuit board pin electrically coupled to a corresponding electrical trace within the circuit board, and at least one cable termination pad, each cable termination pad configured to be electrically and mechanically soldered to a corresponding wire of a cable.Type: ApplicationFiled: March 25, 2022Publication date: September 28, 2023Applicant: Dell Products L.P.Inventors: Jason PRITCHARD, Stephen STRICKLAND
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Patent number: 11758644Abstract: A circuit board may include a traditional via electrically coupled to a first layer of the circuit board and coupled to a second layer of the circuit board and a slotted via formed within the circuit board proximate to the traditional via, the slotted via comprising an opening through a first surface and a second surface of the circuit board and a layer of conductive material formed on interior walls of the opening.Type: GrantFiled: May 13, 2021Date of Patent: September 12, 2023Assignee: Dell Products L.P.Inventors: Jason Pritchard, Charles W. Ziegler, IV, Qianwen Wang, Lingyu Kong
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Patent number: 11706869Abstract: A printed circuit board of an information handling system includes a dielectric layer, adjacent differential pairs, a ground layer, and a ground wall. The adjacent differential pairs are plated on the dielectric layer, and generate crosstalk between each other. The ground wall is in physical communication with and electrically coupled to the ground layer. The ground wall extends substantially perpendicular from the ground layer through the dielectric layer. A top surface of the ground wall is a specific height above a top surface of the adjacent different pairs. The ground wall suppresses the generated crosstalk based on the specific height and a width of the ground wall.Type: GrantFiled: July 28, 2021Date of Patent: July 18, 2023Assignee: Dell Products L.P.Inventors: Lynn Kong, Jason Pritchard, Raymond Pavlak, Jr.
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Publication number: 20230032655Abstract: A printed circuit board of an information handling system includes a dielectric layer, adjacent differential pairs, a ground layer, and a ground wall. The adjacent differential pairs are plated on the dielectric layer, and generate crosstalk between each other. The ground wall is in physical communication with and electrically coupled to the ground layer. The ground wall extends substantially perpendicular from the ground layer through the dielectric layer. A top surface of the ground wall is a specific height above a top surface of the adjacent different pairs. The ground wall suppresses the generated crosstalk based on the specific height and a width of the ground wall.Type: ApplicationFiled: July 28, 2021Publication date: February 2, 2023Inventors: Lynn Kong, Jason Pritchard, Raymond Pavlak, JR.
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Publication number: 20220369452Abstract: A circuit board may include a traditional via electrically coupled to a first layer of the circuit board and coupled to a second layer of the circuit board and a slotted via formed within the circuit board proximate to the traditional via, the slotted via comprising an opening through a first surface and a second surface of the circuit board and a layer of conductive material formed on interior walls of the opening.Type: ApplicationFiled: May 13, 2021Publication date: November 17, 2022Applicant: Dell Products L.P.Inventors: Jason PRITCHARD, Charles W. ZIEGLER, IV, Qianwen WANG, Lingyu KONG
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Patent number: 11444400Abstract: An information handling system includes first and second printed circuit boards (PCBs), and first and second connectors. The first PCB includes a first top surface, a first bottom, and a first plurality of side surfaces extending between the first top and first bottom surfaces. The first connector is embedded within the first PCB, and extends from the first bottom surface toward the first top surface. A first height of the first connector is substantially equal to a first thickness of the first PCB. The second PCB includes a second top surface, a second bottom, and a second plurality of side surfaces extending between the second top and second bottom surfaces. The second connector is embedded within the second PCB, and extends from the second bottom surface toward the second top surface. A second height of the second connector is greater than a second thickness of the second printed circuit board.Type: GrantFiled: December 21, 2020Date of Patent: September 13, 2022Assignee: Dell Products L.P.Inventors: Charles W. Ziegler, IV, Stephen E. Strickland, Jason Pritchard
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Publication number: 20220200179Abstract: An information handling system includes first and second printed circuit boards (PCBs), and first and second connectors. The first PCB includes a first top surface, a first bottom, and a first plurality of side surfaces extending between the first top and first bottom surfaces. The first connector is embedded within the first PCB, and extends from the first bottom surface toward the first top surface. A first height of the first connector is substantially equal to a first thickness of the first PCB. The second PCB includes a second top surface, a second bottom, and a second plurality of side surfaces extending between the second top and second bottom surfaces. The second connector is embedded within the second PCB, and extends from the second bottom surface toward the second top surface. A second height of the second connector is greater than a second thickness of the second printed circuit board.Type: ApplicationFiled: December 21, 2020Publication date: June 23, 2022Inventors: Charles W. Ziegler, IV, Stephen E. Strickland, Jason Pritchard
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Patent number: 11061849Abstract: A system for data communications, comprising an upstream component configured to select an in-band peripheral component interconnect express (PCIe) equalization procedure or an out-of-band PCIe equalization procedure and a downstream component configured to respond to the selected one of the in-band PCIe equalization procedure or the out-of-band PCIe equalization procedure to enable PCIe communications with the upstream component.Type: GrantFiled: October 17, 2019Date of Patent: July 13, 2021Assignee: DELL PRODUCTS L.P.Inventors: Chambers Yin, Jason Pritchard, Andy Qiang Liu, James E. Roche, Lynn Lingyu Kong, Jeremy Qiu
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Patent number: 10999922Abstract: Systems and methods that may be implemented to provide on-board trace impedance testing for a system level board of an information handling system. A printed circuit board (PCB) of the system level board may include built-in test trace circuitry that may be used to measure board trace impedance so that the trace impedance of a fully assembled system level board may be tested and verified for compliance with trace impedance specification, and without requiring any disassembly of the board.Type: GrantFiled: August 7, 2020Date of Patent: May 4, 2021Assignee: Dell Products L.P.Inventors: Charles Ziegler, Jason Pritchard
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Publication number: 20210117363Abstract: A system for data communications, comprising an upstream component configured to select an in-band peripheral component interconnect express (PCIe) equalization procedure or an out-of-band PCIe equalization procedure and a downstream component configured to respond to the selected one of the in-band PCIe equalization procedure or the out-of-band PCIe equalization procedure to enable PCIe communications with the upstream component.Type: ApplicationFiled: October 17, 2019Publication date: April 22, 2021Applicant: DELL PRODUCTS L.P.Inventors: Chambers Yin, Jason Pritchard, Andy Qiang Liu, James E. Roche, Lynn Lingyu Kong, Jeremy Qiu
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Patent number: 9286177Abstract: A computer-executable method, apparatus, or computer program product for automating the analysis of interconnects used with data storage systems, where one or more measured parameters, such as an S-parameter, may be used to determine signal characteristics of the interconnects.Type: GrantFiled: December 28, 2012Date of Patent: March 15, 2016Assignee: EMC CorporationInventors: Jason Pritchard, Rohit Mundra
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Patent number: 8589729Abstract: A data preservation device includes a circuit board configured to be positioned within a memory module slot of a computing device and releasably engage a memory bus of the computing device. A non-volatile memory storage device is electrically coupled to the circuit board. A control circuit is electrically coupled to the circuit board and is configured to read a data portion from the computing device and write the data portion to the non-volatile memory storage device during the occurrence of a power failure event on the computing device. An independent power supply is configured to power the data preservation device during the power failure event.Type: GrantFiled: September 28, 2007Date of Patent: November 19, 2013Assignee: EMC CorporationInventors: Jason Pritchard, Himanshu Agrawal, Michael Robillard, Robert Beauchamp
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Patent number: 8416772Abstract: A link control card for disk drives. The link control card includes: a first connector for carrying relatively high frequency user data and low frequency signals; a diplexer connected to the connector, such diplexer having a first port for the high frequency user data and a second port for the low frequency signals; an optical connector for carrying the relatively high frequency user data; and a high frequency user data communication channel disposed between the diplexer and the disk drives for selectively connected either the first port of the diplexer or the optical connector to the disk drives.Type: GrantFiled: June 26, 2007Date of Patent: April 9, 2013Assignee: EMC CorporationInventor: Jason Pritchard
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Patent number: 8239692Abstract: A system for powering on downstream devices includes a master device; a first slave device; and a first communication link connecting the master device to the slave device for enabling the master device to transmit data signals to the slave device. The master device includes a power-on signal generator for injecting a power-on signal onto the communication link and the first slave device includes a power-on signal receiver for detecting the power-on signal injected on the communication link by the power-on signal generator and powering on the first slave device.Type: GrantFiled: March 31, 2007Date of Patent: August 7, 2012Assignee: EMC CorporationInventors: Michael N. Robillard, Jason Pritchard, Himanshu Agrawal, Jason B. Stock
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Patent number: 7705246Abstract: A differential signal via structure for a printed circuit board having a pair of signal vias extending vertically from a surface of the board to an interior region of the board to contact signal conductors disposed horizontally within the interior region of the board and a pair of ground vias extending vertically from a surface of the circuit board to an interior region of the board to contact ground conductors disposed horizontally within the interior region of the board.Type: GrantFiled: December 28, 2007Date of Patent: April 27, 2010Assignee: EMC CorporationInventors: Jason Pritchard, Michael Gnieski
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Patent number: 7409667Abstract: A technique generates circuit board modeling data for a circuit board structure having multiple layers. The technique includes receiving a set of global circuit board dimension parameters from a user. The set of global circuit board dimension parameters defines a set of global circuit board dimensions of the circuit board structure. The technique further includes forming, for each layer, a set of individual circuit board dimension parameters defining a set of individual circuit board dimensions for that layer based on the set of global circuit board dimension parameters. The technique further includes providing a script for use by a 3D modeling subsystem. The script includes a set of circuit board design values based on the set of individual circuit board dimension parameters formed for each layer. Other properties such as layer width and thickness, via dimensions, etc. are handled in a similar manner.Type: GrantFiled: December 15, 2005Date of Patent: August 5, 2008Assignee: EMC CorporationInventors: Jason Pritchard, Venkat Raghavan Satagopan
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Patent number: 7358752Abstract: A differential signal probe-differential signal launch structure wherein the conductive outer housing of the differential signal probe is disposed on and electrically connected to a conductive ground pad disposed on a printed circuit board. A vertically extending ground via is provided with the conductive pad being electrically connected to the horizontally ground plane conductors through the vertically extending ground via.Type: GrantFiled: March 17, 2006Date of Patent: April 15, 2008Assignee: EMC CorporationInventors: Marlon Ramroopsingh, Jason Pritchard
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Publication number: 20060256980Abstract: A method and apparatus for dynamically controlling the threshold of the onset of dynamics processing in an audio system is provided. In an audio system, the onset of dynamics processing is controlled by varying a control point. The control point is moved by an audio engineer or other means. By changing the position of the control point, the audio engineer is also changing the threshold of onset of dynamics processing, so as to provide a dynamic safety net. Thus, when the engineer moves the control point to a given position, the threshold of onset of dynamics processing moves to a new position which is proportional to the position of the control point, and effectively provides a window through which audio may exit the system unprocessed by the dynamics processor. Regardless of where the control point is positioned, the onset of dynamics processing will depend on the position of the control point and the amount of offset being applied to the threshold.Type: ApplicationFiled: May 11, 2005Publication date: November 16, 2006Inventor: Jason Pritchard
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Patent number: 6182865Abstract: The invention relates to a device for storing a liquid, particularly a dilutable concentrate such as a detergent concentrate or the like, the device being co-operable with a spray dispenser bottle and a spray dispenser head which which together from a spray dispenser, the device comprising: a top wall and a bottom wall, the top wall and bottom wall being separated by one or more side walls, the top and bottom wall each having an opening continuous with a channel running through the device from the top wall opening to the bottom wall opening, whereby the top, bottom and sidewalls together with the channel, define at least one reservoir area of the device wherein liquid is storable, the device further comprising an exit in the device by relative displacement of parts thereof, whereby liquid is releasable from the reservoir area.Type: GrantFiled: March 24, 1998Date of Patent: February 6, 2001Assignee: Deversey Lever, Inc.Inventors: Gerrit Klaas Bunschoten, Norman Jason Pritchard, Fredi Widmer
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Patent number: 6155459Abstract: The invention relates to a device for dosing a predetermined amount of concentrate into a spray dispenser, said device being insertable between a spray head and the spray dispenser, the device comprising:a reservoir chamber for storing a predetermined amount of concentrate;a dosing chamber associated with said reservoir chamber, wherein concentrate is transferable into the dosing chamber from the reservoir chamber, said dosing chamber having such a form as to be able to dose a predetermined amount of concentrate into the spray dispenser.Type: GrantFiled: November 20, 1998Date of Patent: December 5, 2000Assignee: Diversey Lever, Inc.Inventors: Gerrit Klaas Bunschoten, Norman Jason Pritchard