Abstract: A computing system determines a first set of registers having constant next-state functions in the netlist. The computing system identifies an observable gate in fan-out of a register in the first set, wherein an observable gate is a gate that is critical to a verification or synthesis context. The computing system identifies a second set of reducible registers in the fan-in of the observable gate. The computing system modifies at least one of an initial value and a next-state function of at least one reducible register of the second set to reflect an observable value of the at least one reducible register observed at the observable gate. The computing system simplifies one or more logic gates implementing the observable gate and the fan-in of the observable gate by eliminating a reference to a constant next-state function register in the first set of registers.

Abstract: A computing system determines a first set of registers having constant next-state functions in the netlist. The computing system identifies an observable gate in fan-out of a register in the first set, wherein an observable gate is a gate that is critical to a verification or synthesis context. The computing system identifies a second set of reducible registers in the fan-in of the observable gate. The computing system modifies at least one of an initial value and a next-state function of at least one reducible register of the second set to reflect an observable value of the at least one reducible register observed at the observable gate. The computing system simplifies one or more logic gates implementing the observable gate and the fan-in of the observable gate by eliminating a reference to a constant next-state function register in the first set of registers.

Abstract: A logic verification program, method and system provide an efficient behavior when verifying large logic designs. The logic is partitioned by cut-nodes that dominate two or more RANDOMS and a check is performed for a given cut-node to determine whether any of the dominated RANDOMS can be merged to a constant by performing satisfiability checks with each RANDOM merged to a constant, to determine whether a range of output values for the given cut-node has been reduced by merging the RANDOM. If the range is not reduced, the RANDOM can be added to the set of merge-able RANDOMS along with the corresponding constant value. If the range has been reduced, the opposite constant value is tried for a node and if the range is reduced for both constants, then the cut-node is abandoned for merging that dominated RANDOM and the next dominated RANDOM is tried.

Abstract: A logic verification program, method and system provide an efficient behavior when verifying large logic designs. The logic is partitioned by cut-nodes that dominate two or more RANDOMS and a check is performed for a given cut-node to determine whether any of the dominated RANDOMS can be merged to a constant by performing satisfiability checks with each RANDOM merged to a constant, to determine whether a range of output values for the given cut-node has been reduced by merging the RANDOM. If the range is not reduced, the RANDOM can be added to the set of merge-able RANDOMS along with the corresponding constant value. If the range has been reduced, the opposite constant value is tried for a node and if the range is reduced for both constants, then the cut-node is abandoned for merging that dominated RANDOM and the next dominated RANDOM is tried.

Abstract: A computer implemented method for increasing scalability in bounded liveness verification includes receiving, by one or more processors, a counterexample trace showing a bounded liveness failure and a set of parameters associated with the counterexample trace, partitioning the counterexample trace into segments representing bound increments contributing to the bounded liveness failure, selecting, by one or more processors, a time interval during which to repeat input values, wherein the selected time interval correlates to one or more segments, evaluating, by one or more processors, the received counterexample after repeating the selected time interval, determining, by one or more processors, whether the evaluation indicates that the counterexample falsifies a deeper bound with respect to a bound or an unbounded liveness counterexample, and, responsive to determining the evaluation indicates that the counterexample falsifies a deeper bound, providing, by one or more processors, counterexample falsification re

Abstract: Aspects of the present invention include methods, systems and computer program products. The method includes a processor providing a netlist indicative of connectivity and functional states of components of an integrated circuit design; iteratively searching through the netlist at a selected depth to locate errors within the netlist by a plurality of trials, each of the plurality of trials having a plurality of iterations; adaptively adjusting the selected depth depending on any errors within the netlist being located, the selected depth increasing over time from an initial value as between the plurality of iterations; and adaptively adjusting an amount of coverage of the netlist depending on any errors within the netlist being located, the amount of coverage of the netlist decreasing over time from an initial amount as between the plurality of iterations.

Abstract: A computer implemented method for increasing scalability in bounded liveness verification includes receiving, by one or more processors, a counterexample trace showing a bounded liveness failure and a set of parameters associated with the counterexample trace, partitioning the counterexample trace into segments representing bound increments contributing to the bounded liveness failure, selecting, by one or more processors, a time interval during which to repeat input values, wherein the selected time interval correlates to one or more segments, evaluating, by one or more processors, the received counterexample after repeating the selected time interval, determining, by one or more processors, whether the evaluation indicates that the counterexample falsifies a deeper bound with respect to a bound or an unbounded liveness counterexample, and, responsive to determining the evaluation indicates that the counterexample falsifies a deeper bound, providing, by one or more processors, counterexample falsification re

Abstract: Aspects of the present invention include methods, systems and computer program products. The method includes a processor providing a netlist indicative of connectivity and functional states of components of an integrated circuit design; iteratively searching through the netlist at a selected depth to locate errors within the netlist by a plurality of trials, each of the plurality of trials having a plurality of iterations; adaptively adjusting the selected depth depending on any errors within the netlist being located, the selected depth increasing over time from an initial value as between the plurality of iterations; and adaptively adjusting an amount of coverage of the netlist depending on any errors within the netlist being located, the amount of coverage of the netlist decreasing over time from an initial amount as between the plurality of iterations.

Abstract: Aspects of the present invention include methods, systems and computer program products. The method includes a processor providing a netlist indicative of connectivity and functional states of components of an integrated circuit design; iteratively searching through the netlist at a selected depth to locate errors within the netlist by a plurality of trials, each of the plurality of trials having a plurality of iterations; adaptively adjusting the selected depth depending on any errors within the netlist being located, the selected depth increasing over time from an initial value as between the plurality of iterations; and adaptively adjusting an amount of coverage of the netlist depending on any errors within the netlist being located, the amount of coverage of the netlist decreasing over time from an initial amount as between the plurality of iterations.

Abstract: Aspects of the present invention include methods, systems and computer program products. The method includes a processor providing a netlist indicative of connectivity and functional states of components of an integrated circuit design; iteratively searching through the netlist at a selected depth to locate errors within the netlist by a plurality of trials, each of the plurality of trials having a plurality of iterations; adaptively adjusting the selected depth depending on any errors within the netlist being located, the selected depth increasing over time from an initial value as between the plurality of iterations; and adaptively adjusting an amount of coverage of the netlist depending on any errors within the netlist being located, the amount of coverage of the netlist decreasing over time from an initial amount as between the plurality of iterations.

Abstract: Embodiments herein describe a verification process that identifies unate primary inputs in input paths of a property gate. A property gate is logic inserted in a hardware design represented by a netlist which is used to verify the design. Before performing the verification process, a computing system evaluates the netlist to identify the primary inputs in the input paths of the property gate and whether these primary inputs are unate or binate. To do so, in one embodiment, the computing system sets the output of the property gate in an error state and then traverses the input paths of the property gate to identify the values of the logic in the inputs paths that would result in the property gate being in the error state. Based on these polarities, the system can identify the unate and binate primary inputs.

Abstract: Embodiments herein describe a verification process that identifies unate primary inputs in input paths of a property gate. A property gate is logic inserted in a hardware design represented by a netlist which is used to verify the design. Before performing the verification process, a computing system evaluates the netlist to identify the primary inputs in the input paths of the property gate and whether these primary inputs are unate or binate. To do so, in one embodiment, the computing system sets the output of the property gate in an error state and then traverses the input paths of the property gate to identify the values of the logic in the inputs paths that would result in the property gate being in the error state. Based on these polarities, the system can identify the unate and binate primary inputs.

Abstract: Embodiments herein describe a verification process that identifies unate primary inputs in input paths of a property gate. A property gate is logic inserted in a hardware design represented by a netlist which is used to verify the design. Before performing the verification process, a computing system evaluates the netlist to identify the primary inputs in the input paths of the property gate and whether these primary inputs are unate or binate. To do so, in one embodiment, the computing system sets the output of the property gate in an error state and then traverses the input paths of the property gate to identify the values of the logic in the inputs paths that would result in the property gate being in the error state. Based on these polarities, the system can identify the unate and binate primary inputs.

Abstract: Embodiments herein describe a verification process that identifies unate primary inputs in input paths of a property gate. A property gate is logic inserted in a hardware design represented by a netlist which is used to verify the design. Before performing the verification process, a computing system evaluates the netlist to identify the primary inputs in the input paths of the property gate and whether these primary inputs are unate or binate. To do so, in one embodiment, the computing system sets the output of the property gate in an error state and then traverses the input paths of the property gate to identify the values of the logic in the inputs paths that would result in the property gate being in the error state. Based on these polarities, the system can identify the unate and binate primary inputs.

Abstract: A trace of a bounded liveness failure of a system component is received, by one or more processors, along with fairness constraints and liveness assertion conditions. One or more processors generate randomized values for unassigned input values and register values, of the trace, and simulate traversal of each of a sequence of states of the trace. One or more processors determine whether traversing the sequence of states of the trace results in a repetition of a state, and responsive to determining that traversing the sequence of states of the trace does result in a repetition of a state, and the set of fairness constraints are asserted within the repetition of a state, and that the continuous liveness assertion conditions are maintained throughout the repetition of the state, a concrete counterexample of a liveness property of the system component is reported.

Abstract: A method for performing redundancy identification in an integrated circuit design. An optimized gate in a logic circuit is identified. A first netlist with a representation of the logic circuit is generated. An error is induced on the optimized gate. A second netlist is generated from a copy of the first netlist incorporating changes based on the error. Fan-out boundaries of the logic circuit are propagated for the first and second netlists. A redundancy report representing optimization steps performed to obtain the original logic circuit is analyzed to identify which steps are adequate to cause unobservability of the optimized gate. This is done by representing the optimization steps as constraints over the first and second netlists. Responsive to the error becoming undetectable under the constraints derived from the redundancy report, a minimal set of reductions is identified from the first netlist as the reason for unobservability of the optimized gate.

Abstract: A trace of a bounded liveness failure of a system component is received, by one or more processors, along with fairness constraints and liveness assertion conditions. One or more processors generate randomized values for unassigned input values and register values, of the trace, and simulate traversal of each of a sequence of states of the trace. One or more processors determine whether traversing the sequence of states of the trace results in a repetition of a state, and responsive to determining that traversing the sequence of states of the trace does result in a repetition of a state, and the set of fairness constraints are asserted within the repetition of a state, and that the continuous liveness assertion conditions are maintained throughout the repetition of the state, a concrete counterexample of a liveness property of the system component is reported.

Abstract: A method for performing redundancy identification in an integrated circuit design. An optimized gate in a logic circuit is identified. A first netlist with a representation of the logic circuit is generated. An error is induced on the optimized gate. A second netlist is generated from a copy of the first netlist incorporating changes based on the error. Fan-out boundaries of the logic circuit are propagated for the first and second netlists. A redundancy report representing optimization steps performed to obtain the original logic circuit is analyzed to identify which steps are adequate to cause unobservability of the optimized gate. This is done by representing the optimization steps as constraints over the first and second netlists. Responsive to the error becoming undetectable under the constraints derived from the redundancy report, a minimal set of reductions is identified from the first netlist as the reason for unobservability of the optimized gate.

Abstract: A trace of a bounded liveness failure of a system component is received, by one or more processors, along with fairness constraints and liveness assertion conditions. One or more processors generate randomized values for unassigned input values and register values, of the trace, and simulate traversal of each of a sequence of states of the trace. One or more processors determine whether traversing the sequence of states of the trace results in a repetition of a state, and responsive to determining that traversing the sequence of states of the trace does result in a repetition of a state, and the set of fairness constraints are asserted within the repetition of a state, and that the continuous liveness assertion conditions are maintained throughout the repetition of the state, a concrete counterexample of a liveness property of the system component is reported.

Abstract: A trace of a bounded liveness failure of a system component is received, by one or more processors, along with fairness constraints and liveness assertion conditions. One or more processors generate randomized values for unassigned input values and register values, of the trace, and simulate traversal of each of a sequence of states of the trace. One or more processors determine whether traversing the sequence of states of the trace results in a repetition of a state, and responsive to determining that traversing the sequence of states of the trace does result in a repetition of a state, and the set of fairness constraints are asserted within the repetition of a state, and that the continuous liveness assertion conditions are maintained throughout the repetition of the state, a concrete counterexample of a liveness property of the system component is reported.