Patents by Inventor Jason R. Fender
Jason R. Fender has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10366986Abstract: A monolithic integrated circuit includes first and second pluralities of parallel-connected transistor elements (e.g., transistor fingers). To spread heat in the IC, the first and second pluralities of transistor elements are interleaved with each other and arranged in a first row. The IC also may include third and fourth pluralities of parallel-connected transistor elements arranged in a second row. The transistor elements in the first row may be series and shunt transistors of an RF switch transmit path, and the transistor elements in the second row may be series and shunt transistors of an RF switch receive path. During a transmit mode of operation, the series transistors in the transmit path and the shunt transistors in the receive path are closed. During a receive mode of operation, the shunt transistors in the transmit path and the series transistors in the receive path are closed.Type: GrantFiled: March 20, 2019Date of Patent: July 30, 2019Assignee: NXP USA, Inc.Inventors: Jason R. Fender, Michael L. Fraser, Frank E. Danaher
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Publication number: 20190221561Abstract: A monolithic integrated circuit includes first and second pluralities of parallel-connected transistor elements (e.g., transistor fingers). To spread heat in the IC, the first and second pluralities of transistor elements are interleaved with each other and arranged in a first row. The IC also may include third and fourth pluralities of parallel-connected transistor elements arranged in a second row. The transistor elements in the first row may be series and shunt transistors of an RF switch transmit path, and the transistor elements in the second row may be series and shunt transistors of an RF switch receive path. During a transmit mode of operation, the series transistors in the transmit path and the shunt transistors in the receive path are closed. During a receive mode of operation, the shunt transistors in the transmit path and the series transistors in the receive path are closed.Type: ApplicationFiled: March 20, 2019Publication date: July 18, 2019Inventors: Jason R. Fender, Michael L. Fraser, Frank E. Danaher
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Patent number: 10318447Abstract: A Universal SPI Interface is provided that is compatible, without the need for additional interface logic or software, with the SPI bus, existing DSA and other serial busses similar to (but not directly compatible with) the SPI bus, and parallel busses requiring compatibility with 74xx 164-type signaling. In an additional aspect, a reduced-pincount Universal SPI Interface is provided that provides the same universal interface, but using fewer external output pins. The Universal SPI Interface includes multiple latches, buffers, and in an alternative embodiment, a multiplexer, configured together such that a Universal SPI Interface is provided that can be readily reconfigured using only input signals to provide compatibility across multiple bus interfaces.Type: GrantFiled: April 18, 2017Date of Patent: June 11, 2019Assignee: NXP USA, Inc.Inventors: Nicholas J. Spence, Jason R. Fender, Michael L. Fraser
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Patent number: 10283500Abstract: A monolithic integrated circuit includes first and second pluralities of parallel-connected transistor elements (e.g., transistor fingers). To spread heat in the IC, the first and second pluralities of transistor elements are interleaved with each other and arranged in a first row. The IC also may include third and fourth pluralities of parallel-connected transistor elements arranged in a second row. The transistor elements in the first row may be series and shunt transistors of an RF switch transmit path, and the transistor elements in the second row may be series and shunt transistors of an RF switch receive path. During a transmit mode of operation, the series transistors in the transmit path and the shunt transistors in the receive path are closed. During a receive mode of operation, the shunt transistors in the transmit path and the series transistors in the receive path are closed.Type: GrantFiled: September 29, 2017Date of Patent: May 7, 2019Assignee: NXP USA, Inc.Inventors: Michael L. Fraser, Frank E. Danaher, Jason R. Fender
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Publication number: 20180033787Abstract: A monolithic integrated circuit includes first and second pluralities of parallel-connected transistor elements (e.g., transistor fingers). To spread heat in the IC, the first and second pluralities of transistor elements are interleaved with each other and arranged in a first row. The IC also may include third and fourth pluralities of parallel-connected transistor elements arranged in a second row. The transistor elements in the first row may be series and shunt transistors of an RF switch transmit path, and the transistor elements in the second row may be series and shunt transistors of an RF switch receive path. During a transmit mode of operation, the series transistors in the transmit path and the shunt transistors in the receive path are closed. During a receive mode of operation, the shunt transistors in the transmit path and the series transistors in the receive path are closed.Type: ApplicationFiled: September 29, 2017Publication date: February 1, 2018Inventors: Michael L. FRASER, Frank E. DANAHER, Jason R. FENDER
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Patent number: 9780090Abstract: A monolithic integrated circuit includes first and second pluralities of parallel-connected transistor elements (e.g., transistor fingers). To spread heat in the IC, the first and second pluralities of transistor elements are interleaved with each other and arranged in a first row. The IC also may include third and fourth pluralities of parallel-connected transistor elements arranged in a second row. The transistor elements in the first row may be series and shunt transistors of an RF switch transmit path, and the transistor elements in the second row may be series and shunt transistors of an RF switch receive path. During a transmit mode of operation, the series transistors in the transmit path and the shunt transistors in the receive path are closed. During a receive mode of operation, the shunt transistors in the transmit path and the series transistors in the receive path are closed.Type: GrantFiled: October 19, 2015Date of Patent: October 3, 2017Assignee: NXP USA, INC.Inventors: Michael L. Fraser, Frank E. Danaher, Jason R. Fender
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Publication number: 20170220519Abstract: A Universal SPI Interface is provided that is compatible, without the need for additional interface logic or software, with the SPI bus, existing DSA and other serial busses similar to (but not directly compatible with) the SPI bus, and parallel busses requiring compatibility with 74xx164-type signaling. In an additional aspect, a red Universal SPI Interface is provided that provides the same universal interface, but using fewer external output pins. The Universal SPI Interface includes multiple latches, buffers, and in an alternative embodiment, a multiplexer, configured together such that a Universal SPI interface is provided that can be readily reconfigured using only input signals to provide compatibility across multiple bus interfaces.Type: ApplicationFiled: April 18, 2017Publication date: August 3, 2017Inventors: Nicholas J. Spence, Jason R. Fender, Michael L. Fraser
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Patent number: 9658971Abstract: A Universal SPI Interface is provided that is compatible, without the need for additional interface logic or software, with the SPI bus, existing DSA and other serial busses similar to (but not directly compatible with) the SPI bus, and parallel busses requiring compatibility with 74xx164-type signaling. In an additional aspect, a reduced-pincount Universal SPI Interface is provided that provides the same universal interface, but using fewer external output pins. The Universal SPI Interface includes multiple latches, buffers, and in an alternative embodiment, a multiplexer, configured together such that a Universal SPI interface is provided that can be readily reconfigured using only input signals to provide compatibility across multiple bus interfaces.Type: GrantFiled: September 11, 2013Date of Patent: May 23, 2017Assignee: NXP USA, Inc.Inventors: Nicholas J. Spence, Jason R. Fender, Michael L. Fraser
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Publication number: 20170110451Abstract: A monolithic integrated circuit includes first and second pluralities of parallel-connected transistor elements (e.g., transistor fingers). To spread heat in the IC, the first and second pluralities of transistor elements are interleaved with each other and arranged in a first row. The IC also may include third and fourth pluralities of parallel-connected transistor elements arranged in a second row. The transistor elements in the first row may be series and shunt transistors of an RF switch transmit path, and the transistor elements in the second row may be series and shunt transistors of an RF switch receive path. During a transmit mode of operation, the series transistors in the transmit path and the shunt transistors in the receive path are closed. During a receive mode of operation, the shunt transistors in the transmit path and the series transistors in the receive path are closed.Type: ApplicationFiled: October 19, 2015Publication date: April 20, 2017Inventors: MICHAEL L. FRASER, FRANK E. DANAHER, JASON R. FENDER
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Patent number: 9070683Abstract: An electronic apparatus includes a semiconductor substrate, outer and inner guard rings disposed along a periphery of the semiconductor substrate, and first and second contact pads electrically coupled to the outer and inner guard rings, respectively. The outer and inner guard rings are electrically coupled to one another to define a conduction path between the first and second contact pads. Each of the outer and inner guard rings includes an Ohmic metal layer having a plurality of gaps and further includes conductive bridges across the gaps. The gaps of the outer guard ring are laterally offset from the gaps of the inner guard ring such that the Ohmic metal layers of the outer and inner guard rings laterally overlap.Type: GrantFiled: June 20, 2013Date of Patent: June 30, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Jason R. Fender, Ngai Ming Lau
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Publication number: 20150074319Abstract: A Universal SPI Interface is provided that is compatible, without the need for additional interface logic or software, with the SPI bus, existing DSA and other serial busses similar to (but not directly compatible with) the SPI bus, and parallel busses requiring compatibility with 74xx164-type signaling. In an additional aspect, a reduced-pincount Universal SPI Interface is provided that provides the same universal interface, but using fewer external output pins. The Universal SPI Interface includes multiple latches, buffers, and in an alternative embodiment, a multiplexer, configured together such that a Universal SPI interface is provided that can be readily reconfigured using only input signals to provide compatibility across multiple bus interfaces.Type: ApplicationFiled: September 11, 2013Publication date: March 12, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Nicholas J. Spence, Jason R. Fender, Michael L. Fraser
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Publication number: 20140375341Abstract: An electronic apparatus includes a semiconductor substrate, outer and inner guard rings disposed along a periphery of the semiconductor substrate, and first and second contact pads electrically coupled to the outer and inner guard rings, respectively. The outer and inner guard rings are electrically coupled to one another to define a conduction path between the first and second contact pads. Each of the outer and inner guard rings includes an Ohmic metal layer having a plurality of gaps and further includes conductive bridges across the gaps. The gaps of the outer guard ring are laterally offset from the gaps of the inner guard ring such that the Ohmic metal layers of the outer and inner guard rings laterally overlap.Type: ApplicationFiled: June 20, 2013Publication date: December 25, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Jason R. Fender, Ngai Ming Lau
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Patent number: 7935607Abstract: According to one aspect of the present invention, a method of forming a microelectronic assembly, such as an integrated passive device (IPD) (72), is provided. An insulating dielectric layer (32) having a thickness (36) of at least 4 microns is formed over a silicon substrate (20). At least one passive electronic component (62) is formed over the insulating dielectric layer (32).Type: GrantFiled: April 9, 2007Date of Patent: May 3, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Jonathan K. Abrokwah, Keri L. Costello, James G. Cotronakis, Terry K. Daly, Jason R. Fender, Adolfo G. Reyes
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Patent number: 7723224Abstract: A method is provided for forming a microelectronic assembly. A contact structure (46) is formed over a first side of a first substrate (20) having a microelectronic device formed over a second side thereof. The contact structure is electrically connected to the microelectronic device. A non-solderable layer (52) is formed over at least a portion of the contact structure and at least a portion of the first substrate. The contact structure and a second substrate (62) are interconnected with solder (68).Type: GrantFiled: June 14, 2006Date of Patent: May 25, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Darrell G. Hill, Philip H. Bowles, Jan Campbell, Terry K. Daly, Jason R. Fender, Lakshmi N. Ramanathan, Neil T. Tracht
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Publication number: 20090236689Abstract: According to one aspect of the present invention, a method of forming a microelectronic assembly, such as an integrated passive device (72), is provided. An insulating initial dielectric layer (32) comprising charge trapping films of, for example, aluminum nitride or silicon nitride or silicon oxide or a combination thereof, is formed over a silicon substrate (20). At least one passive electronic component (62) is formed over the initial dielectric layer (32). In an embodiment where silicon nitride or oxide is used in the initial dielectric layer (32) in contact with the silicon substrate (20), it is desirable to pre-treat the silicon surface (22) by exposing it to a surface damage causing treatment (e.g. an argon plasma) prior to depositing the initial dielectric layer, to assist in providing carrier depletion near the silicon surface around zero bias. RF loss in integrated passive devices using such silicon substrates is equal or lower than that obtained with GaAs substrates.Type: ApplicationFiled: March 24, 2008Publication date: September 24, 2009Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Terry K. Daly, Keri L. Costello, James G. Cotronakis, Jason R. Fender, Jeff S. Hughes, Agni Mitra, Adolfo C. Reyes
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Publication number: 20080246114Abstract: According to one aspect of the present invention, a method of forming a microelectronic assembly, such as an integrated passive device (IPD) (72), is provided. An insulating dielectric layer (32) having a thickness (36) of at least 4 microns is formed over a silicon substrate (20). At least one passive electronic component (62) is formed over the insulating dielectric layer (32).Type: ApplicationFiled: April 9, 2007Publication date: October 9, 2008Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Jonathan K. Abrokwah, Keri L. Costello, James G. Cotronakis, Terry K. Daly, Jason R. Fender, Adolfo C. Reyes
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Publication number: 20070293033Abstract: A method is provided for forming a microelectronic assembly. A contact structure (46) is formed over a first side of a first substrate (20) having a microelectronic device formed over a second side thereof. The contact structure is electrically connected to the microelectronic device. A non-solderable layer (52) is formed over at least a portion of the contact structure and at least a portion of the first substrate. The contact structure and a second substrate (62) are interconnected with solder (68).Type: ApplicationFiled: June 14, 2006Publication date: December 20, 2007Inventors: Darrell G. Hill, Philip H. Bowles, Jan Campbell, Terry K. Daly, Jason R. Fender, Lakshmi N. Ramanathan, Neil T. Tracht