Patents by Inventor Jason R. Gonzalez

Jason R. Gonzalez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PRINTED CIRCUIT BOARD HAVING EMBEDDED DIES AND METHOD OF FORMING SAME
    Publication number: 20130270718
    Abstract: A package includes a printed circuit board (PCB) having a first side and a second side and a thickness between the first side and the second side and a stacked die including a top die mounted on a bottom die, the bottom die being at least partially embedded in the PCB. Also a method of forming a package that includes forming an opening in a top surface of the PCB layer, placing a stacked die including a top die stacked on a bottom die into the opening, laminating the PCB layer to form a laminate layer, and forming an electrical connection with the stacked die.
    Type: Application
    Filed: June 17, 2013
    Publication date: October 17, 2013
    Inventors: Fifin Sweeney, Jason R. Gonzalez
  • Printed circuit board having embedded dies and method of forming same
    Patent number: 8476750
    Abstract: A package includes a printed circuit board (PCB) having a first side and a second side and a thickness between the first side and the second side and a stacked die including a top die mounted on a bottom die, the bottom die being at least partially embedded in the PCB. Also a method of forming a package that includes forming an opening in a top surface of the PCB layer, placing a stacked die including a top die stacked on a bottom die into the opening, laminating the PCB layer to form a laminate layer, and forming an electrical connection with the stacked die.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: July 2, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Fifin Sweeney, Jason R. Gonzalez
  • Printed Circuit Board having Embedded Dies and Method of Forming Same
    Publication number: 20110140257
    Abstract: A package includes a printed circuit board (PCB) having a first side and a second side and a thickness between the first side and the second side and a stacked die including a top die mounted on a bottom die, the bottom die being at least partially embedded in the PCB. Also a method of forming a package that includes forming an opening in a top surface of the PCB layer, placing a stacked die including a top die stacked on a bottom die into the opening, laminating the PCB layer to form a laminate layer, and forming an electrical connection with the stacked die.
    Type: Application
    Filed: December 10, 2009
    Publication date: June 16, 2011
    Applicant: QUALCOMM Incorporated
    Inventors: Fifin Sweeney, Jason R. Gonzalez
  • Capacitor Die Design for Small Form Factors
    Publication number: 20100123215
    Abstract: A semiconductor package has a capacitor die and a packaging substrate. The capacitor die is coupled to circuitry on a front or back side of a die coupled to the packaging substrate for providing decoupling capacitance. In one example, the capacitor die is coupled to a land side of the packaging substrate in an area depopulated of a packaging array and adjacent to the packaging array. In another example, the capacitor die may be stacked on the die and coupled through wire bonds to circuitry on the die. The capacitor die reduces impedance of the integrated circuit allowing operation at higher frequencies.
    Type: Application
    Filed: November 18, 2009
    Publication date: May 20, 2010
    Applicant: QUALCOMM INCORPORATED
    Inventors: Yuancheng Christopher Pan, Fifin Sweeney, Charlie Paynter, Kevin R. Bowles, Jason R. Gonzalez
  • Pocket towel
    Patent number: D488662
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: April 20, 2004
    Inventor: Jason R. Gonzalez