Abstract: A system and method is disclosed for designing a dynamic circuit in a silicon-on-insulator (SOI) process comprising the steps of representing the dynamic circuit using at least one logic circuit, wherein the at least one logic circuit is selected from a group consisting of: an OR circuit with a DNG field effect transistor (FET), an OR circuit, and an AND circuit, and wherein the at least one logic circuit is selected according to body voltage characteristics of each circuit in the group.

Abstract: A system and method for generating dynamic circuit design guidelines is disclosed comprising modeling a dynamic circuit using one of a plurality of modeling circuit types, simulating the modeled dynamic circuit, extracting selected information from raw data measured during the simulating step, and analyzing the selected information to create the dynamic circuit design guidelines.

Abstract: A system and method is disclosed for designing a dynamic circuit in a silicon-on-insulator (SOI) process comprising the steps of representing the dynamic circuit using at least one logic circuit, wherein the at least one logic circuit is selected from a group consisting of: an OR circuit with a DNG field effect transistor (FET), an OR circuit, and an AND circuit, and wherein the at least one logic circuit is selected according to body voltage characteristics of each circuit in the group.

Abstract: A system and method for generating dynamic circuit design guidelines is disclosed comprising modeling a dynamic circuit using one of a plurality of modeling circuit types, simulating the modeled dynamic circuit, extracting selected information from raw data measured during the simulating step, and analyzing the selected information to create the dynamic circuit design guidelines.

Abstract: The present invention is directed to a system and method for preserving voltage levels in a logic circuit wherein the system preferably includes a precharge circuit for raising a voltage of first connection points, which are preferably drains, of at least two transistors to a logical high level. Preferably, a plurality of electrically separate interstitial nodes are provided within the logic circuit. Each interstitial node is preferably connected to a second connection point, which is preferably a source, of at least one of the transistors. Preferably, a transistor or other switching mechanism is interposed between each of the interstitial nodes and electrical ground for selectively establishing a connection to ground during an evaluate state or phase of a logic circuit and establishing an open circuit during a precharge state or phase of the logic circuit.

Abstract: An integrated circuit having programmable fuse provisions separate from critical circuitry, for storing chip specific operational information necessary for proper integrated circuit operation. These separate provisions include a fuse block which contains the programmable fuse. The fuse block is positioned adjacent to a current source input which is used to provide current to the programmable fuse for purposes of programming the programmable fuse with the chip specific operational information.