Abstract: Systems and methods may provide for detecting a pending write operation directed to a target memory region and determining whether the target memory region satisfies a degradation condition in response to the pending write operation. Additionally, the target memory region may be automatically reconfigured as a cold storage region if the target memory region satisfies the degradation condition. In one example, determining whether the target memory region satisfies the degradation condition includes updating the number of write operations directed to the target memory region based on the pending write operation and comparing the number of write operations to an offset value, wherein the degradation condition is satisfied if the number of write operations exceeds the offset value.

Abstract: A processor including a first distributed shift generator associated with a first time domain, wherein the first distributed shift generator is coupled to a first group of scan chains, the first distributed shift generator to send a shift-enable-flop signal to be received by the first group of scan chains. The processor including a second distributed shift generator associated with a second time domain, wherein the second distributed shift generator is coupled to a second group of scan chains, the second distributed shift generator to send a shift-enable-flop signal to be received by the second group of scan chains. The processor including a scan test controller coupled to the first and second distributed shift generators, the scan test controller to provide clocking signals for the first time domain and the second time domain for performing an at-speed test of circuits coupled to the first group of scan chains.

Abstract: A combinatorial at-speed scan testing. A processor including a plurality of distributed slave counters. Each distributed slave counter coupled to a group of scan chains, each distributed slave counter to generate shift-enable-flop signals to be received by the group of scan chains coupled to each distributed slave counter, the shift-enable-flop signals based at least in part on an external shift-enable signal received by the processor. A scan test controller coupled to the plurality of distributed slave counters to provide control signals to the plurality of distributed slave counters to perform an at-speed test of the processor.