Patents by Inventor Jason R. White
Jason R. White has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11972493Abstract: A system and method in accordance with example embodiments for comprehensive sales and service data reporting. Sales and service events that take place at a front end branch of an enterprise may be input into a front end system and transmitted to a backend system where various modules then use the front end system data to generate various data and reports to display various data, such as, for example, sales incentive metrics and key performance indicators.Type: GrantFiled: September 20, 2021Date of Patent: April 30, 2024Assignee: CAPITAL ONE SERVICES, LLCInventors: Kenneth A. Windbeck, Emil W. Philips, Corey J. Barrett, Jason R. Kary, Sean J. White, Paula Edwards-Seal, Elizabeth Hoffman
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Patent number: 11789965Abstract: Various methods and apparatuses are described for performing high speed format translations of incoming data, where the incoming data is arranged in a delimited data format. As an example, the data in the delimited data format can be translated to a structured format such as a fixed field format using pipelined operations. A reconfigurable logic device can be used in exemplary embodiments as a platform for the format translation.Type: GrantFiled: April 13, 2020Date of Patent: October 17, 2023Assignee: IP Reservoir, LLCInventors: Michael John Henrichs, Joseph M. Lancaster, Roger Dean Chamberlain, Jason R. White, Kevin Brian Sprague, Terry Tidwell
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Patent number: 11677417Abstract: Disclosed herein are methods and systems for hardware-accelerating various data processing operations in a rule-based decision-making system such as a business rules engine, an event stream processor, and a complex event stream processor. Preferably, incoming data streams are checked against a plurality of rule conditions. Among the data processing operations that are hardware-accelerated include rule condition check operations, filtering operations, and path merging operations. The rule condition check operations generate rule condition check results for the processed data streams, wherein the rule condition check results are indicative of any rule conditions which have been satisfied by the data streams. The generation of such results with a low degree of latency provides enterprises with the ability to perform timely decision-making based on the data present in received data streams.Type: GrantFiled: March 29, 2021Date of Patent: June 13, 2023Assignee: IP Reservoir, LLCInventors: Ronald S. Indeck, David Mark Indeck, Naveen Singla, Jason R. White
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Publication number: 20210218417Abstract: Disclosed herein are methods and systems for hardware-accelerating various data processing operations in a rule-based decision-making system such as a business rules engine, an event stream processor, and a complex event stream processor. Preferably, incoming data streams are checked against a plurality of rule conditions. Among the data processing operations that are hardware-accelerated include rule condition check operations, filtering operations, and path merging operations. The rule condition check operations generate rule condition check results for the processed data streams, wherein the rule condition check results are indicative of any rule conditions which have been satisfied by the data streams. The generation of such results with a low degree of latency provides enterprises with the ability to perform timely decision-making based on the data present in received data streams.Type: ApplicationFiled: March 29, 2021Publication date: July 15, 2021Inventors: Ronald S. Indeck, David Mark Indeck, Naveen Singla, Jason R. White
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Patent number: 10965317Abstract: Disclosed herein are methods and systems for hardware-accelerating various data processing operations in a rule-based decision-making system such as a business rules engine, an event stream processor, and a complex event stream processor. Preferably, incoming data streams are checked against a plurality of rule conditions. Among the data processing operations that are hardware-accelerated include rule condition check operations, filtering operations, and path merging operations. The rule condition check operations generate rule condition check results for the processed data streams, wherein the rule condition check results are indicative of any rule conditions which have been satisfied by the data streams. The generation of such results with a low degree of latency provides enterprises with the ability to perform timely decision-making based on the data present in received data streams.Type: GrantFiled: September 9, 2019Date of Patent: March 30, 2021Assignee: IP Reservoir, LLCInventors: Ronald S. Indeck, David Mark Indeck, Naveen Singla, Jason R. White
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Patent number: 10949442Abstract: Various methods and apparatuses are described for performing high speed format translations of incoming data, where the incoming data is arranged in a delimited data format. As an example, the data in the delimited data format can be translated to a mapped variable field format using pipelined operations. A reconfigurable logic device can be used in exemplary embodiments as a platform for the format translation.Type: GrantFiled: November 29, 2018Date of Patent: March 16, 2021Assignee: IP Reservoir, LLCInventors: Michael John Henrichs, Joseph M. Lancaster, Roger Dean Chamberlain, Jason R. White, Kevin Brian Sprague, Terry Tidwell
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Publication number: 20200242126Abstract: Various methods and apparatuses are described for performing high speed format translations of incoming data, where the incoming data is arranged in a delimited data format. As an example, the data in the delimited data format can be translated to a structured format such as a fixed field format using pipelined operations. A reconfigurable logic device can be used in exemplary embodiments as a platform for the format translation.Type: ApplicationFiled: April 13, 2020Publication date: July 30, 2020Inventors: Michael John Henrichs, Joseph M. Lancaster, Roger Dean Chamberlain, Jason R. White, Kevin Brian Sprague, Terry Tidwell
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Patent number: 10621192Abstract: Various methods and apparatuses are described for performing high speed format translations of incoming data, where the incoming data is arranged in a delimited data format. As an example, the data in the delimited data format can be translated to a fixed field format using pipelined operations. A reconfigurable logic device can be used in exemplary embodiments as a platform for the format translation.Type: GrantFiled: April 17, 2017Date of Patent: April 14, 2020Assignee: IP Resevoir, LLCInventors: Michael John Henrichs, Joseph M. Lancaster, Roger Dean Chamberlain, Jason R. White, Kevin Brian Sprague, Terry Tidwell
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Publication number: 20200007157Abstract: Disclosed herein are methods and systems for hardware-accelerating various data processing operations in a rule-based decision-making system such as a business rules engine, an event stream processor, and a complex event stream processor. Preferably, incoming data streams are checked against a plurality of rule conditions. Among the data processing operations that are hardware-accelerated include rule condition check operations, filtering operations, and path merging operations. The rule condition check operations generate rule condition check results for the processed data streams, wherein the rule condition check results are indicative of any rule conditions which have been satisfied by the data streams. The generation of such results with a low degree of latency provides enterprises with the ability to perform timely decision-making based on the data present in received data streams.Type: ApplicationFiled: September 9, 2019Publication date: January 2, 2020Inventors: Ronald S. Indeck, David Mark Indeck, Naveen Singla, Jason R. White
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Patent number: 10411734Abstract: Disclosed herein are methods and systems for hardware-accelerating various data processing operations in a rule-based decision-making system such as a business rules engine, an event stream processor, and a complex event stream processor. Preferably, incoming data streams are checked against a plurality of rule conditions. Among the data processing operations that are hardware-accelerated include rule condition check operations, filtering operations, and path merging operations. The rule condition check operations generate rule condition check results for the processed data streams, wherein the rule condition check results are indicative of any rule conditions which have been satisfied by the data streams. The generation of such results with a low degree of latency provides enterprises with the ability to perform timely decision-making based on the data present in received data streams.Type: GrantFiled: December 17, 2018Date of Patent: September 10, 2019Assignee: IP RESERVOIR, LLCInventors: Ronald S. Indeck, David Mark Indeck, Naveen Singla, Jason R. White
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Publication number: 20190123764Abstract: Disclosed herein are methods and systems for hardware-accelerating various data processing operations in a rule-based decision-making system such as a business rules engine, an event stream processor, and a complex event stream processor. Preferably, incoming data streams are checked against a plurality of rule conditions. Among the data processing operations that are hardware-accelerated include rule condition check operations, filtering operations, and path merging operations. The rule condition check operations generate rule condition check results for the processed data streams, wherein the rule condition check results are indicative of any rule conditions which have been satisfied by the data streams. The generation of such results with a low degree of latency provides enterprises with the ability to perform timely decision-making based on the data present in received data streams.Type: ApplicationFiled: December 17, 2018Publication date: April 25, 2019Inventors: Ronald S. Indeck, David Mark Indeck, Naveen Singla, Jason R. White
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Publication number: 20190108177Abstract: Various methods and apparatuses are described for performing high speed format translations of incoming data, where the incoming data is arranged in a delimited data format. As an example, the data in the delimited data format can be translated to a mapped variable field format using pipelined operations. A reconfigurable logic device can be used in exemplary embodiments as a platform for the format translation.Type: ApplicationFiled: November 29, 2018Publication date: April 11, 2019Inventors: Michael John Henrichs, Joseph M. Lancaster, Roger Dean Chamberlain, Jason R. White, Kevin Brian Sprague, Terry Tidwell
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Patent number: 10158377Abstract: Disclosed herein are methods and systems for hardware-accelerating various data processing operations in a rule-based decision-making system such as a business rules engine, an event stream processor, and a complex event stream processor. Preferably, incoming data streams are checked against a plurality of rule conditions. Among the data processing operations that are hardware-accelerated include rule condition check operations, filtering operations, and path merging operations. The rule condition check operations generate rule condition check results for the processed data streams, wherein the rule condition check results are indicative of any rule conditions which have been satisfied by the data streams. The generation of such results with a low degree of latency provides enterprises with the ability to perform timely decision-making based on the data present in received data streams.Type: GrantFiled: January 12, 2017Date of Patent: December 18, 2018Assignee: IP RESERVOIR, LLCInventors: Ronald S. Indeck, David Mark Indeck, Naveen Singla, Jason R. White
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Patent number: 10146845Abstract: Various methods and apparatuses are described for performing high speed format translations of incoming data, where the incoming data is arranged in a delimited data format. As an example, the data in the delimited data format can be translated to a mapped variable field format using pipelined operations. A reconfigurable logic device can be used in exemplary embodiments as a platform for the format translation.Type: GrantFiled: October 22, 2013Date of Patent: December 4, 2018Assignee: IP RESERVOIR, LLCInventors: Michael John Henrichs, Joseph M. Lancaster, Roger Dean Chamberlain, Jason R. White, Kevin Brian Sprague, Terry Tidwell
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Publication number: 20170220655Abstract: Various methods and apparatuses are described for performing high speed format translations of incoming data, where the incoming data is arranged in a delimited data format. As an example, the data in the delimited data format can be translated to a fixed field format using pipelined operations. A reconfigurable logic device can be used in exemplary embodiments as a platform for the format translation.Type: ApplicationFiled: April 17, 2017Publication date: August 3, 2017Inventors: Michael John Henrichs, Joseph M. Lancaster, Roger Dean Chamberlain, Jason R. White, Kevin Brian Sprague, Terry Tidwell
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Publication number: 20170123866Abstract: Disclosed herein are methods and systems for hardware-accelerating various data processing operations in a rule-based decision-making system such as a business rules engine, an event stream processor, and a complex event stream processor. Preferably, incoming data streams are checked against a plurality of rule conditions. Among the data processing operations that are hardware-accelerated include rule condition check operations, filtering operations, and path merging operations. The rule condition check operations generate rule condition check results for the processed data streams, wherein the rule condition check results are indicative of any rule conditions which have been satisfied by the data streams. The generation of such results with a low degree of latency provides enterprises with the ability to perform timely decision-making based on the data present in received data streams.Type: ApplicationFiled: January 12, 2017Publication date: May 4, 2017Inventors: Ronald S. Indeck, David Mark Indeck, Naveen Singla, Jason R. White
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Patent number: 9633093Abstract: Various methods and apparatuses are described for performing high speed format translations of incoming data, where the incoming data is arranged in a delimited data format. As an example, the data in the delimited data format can be translated to a fixed field format using pipelined operations. A reconfigurable logic device can be used in exemplary embodiments as a platform for the format translation.Type: GrantFiled: October 22, 2013Date of Patent: April 25, 2017Assignee: IP Reservoir, LLCInventors: Michael John Henrichs, Joseph M. Lancaster, Roger Dean Chamberlain, Jason R. White, Kevin Brian Sprague, Terry Tidwell
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Patent number: 9547824Abstract: Disclosed herein is a method and apparatus for hardware-accelerating various data quality checking operations. Incoming data streams can be processed with respect to a plurality of data quality check operations using offload engines (e.g., reconfigurable logic such as field programmable gate arrays (FPGAs)). Accelerated data quality checking can be highly advantageous for use in connection with Extract, Transfer, and Load (ETL) systems.Type: GrantFiled: February 5, 2013Date of Patent: January 17, 2017Assignee: IP Reservoir, LLCInventors: Ronald S. Indeck, David Mark Indeck, Naveen Singla, Jason R. White
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Patent number: 8983063Abstract: An encryption technique is disclosed for encrypting a plurality of data blocks of a data segment where the encryption selectively switches between a blockwise independent randomized (BIR) encryption mode and a cipher block chaining (CBC) encryption mode based on a configurable feedback stride. A corresponding decryption technique is also disclosed.Type: GrantFiled: May 16, 2014Date of Patent: March 17, 2015Assignee: IP Reservoir, LLCInventors: David E. Taylor, Ronald S. Indeck, Jason R. White, Roger D. Chamberlain
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Publication number: 20150055776Abstract: An encryption technique is disclosed for encrypting a plurality of data blocks of a data segment where the encryption selectively switches between a blockwise independent randomized (BIR) encryption mode and a cipher block chaining (CBC) encryption mode based on a configurable feedback stride. A corresponding decryption technique is also disclosed.Type: ApplicationFiled: May 16, 2014Publication date: February 26, 2015Applicant: IP Reservoir, LLCInventors: David E. Taylor, Ronald S. Indeck, Jason R. White, Roger D. Chamberlain