Abstract: A power supply apparatus includes first and second parallel-connected uninterruptible power supplies (UPSs), each including an AC/DC converter circuit and a DC/AC converter circuit having an input coupled to an output of the AC/DC converter circuit by a DC link, inputs of the AC/DC converter circuits of the first and second UPSs connected in common to an AC source and outputs of the DC/AC converter circuits of the first and second UPSs connected in common to a load. The first and second UPSs are configured to support a test mode wherein the first UPS is test loaded by transferring power from the output of the DC/AC converter circuit of the first UPS to the output of the DC/AC converter circuit of the second UPS. The first UPS may be configured to provide power to the load concurrent with test loading by the second UPS.

Abstract: A power supply apparatus includes first and second parallel-connected uninterruptible power supplies (UPSs), each including an AC/DC converter circuit and a DC/AC converter circuit having an input coupled to an output of the AC/DC converter circuit by a DC link, inputs of the AC/DC converter circuits of the first and second UPSs connected in common to an AC source and outputs of the DC/AC converter circuits of the first and second UPSs connected in common to a load. The first and second UPSs are configured to support a test mode wherein the first UPS is test loaded by transferring power from the output of the DC/AC converter circuit of the first UPS to the output of the DC/AC converter circuit of the second UPS. The first UPS may be configured to provide power to the load concurrent with test loading by the second UPS.

Abstract: Paralleled uninterruptible power supplies (UPSs) including respective pulse-width modulation (PWM) power converter circuits coupled in common to an AC load bus have PWM cycles that are synchronized. In particular, sampling of control inputs of the PWM power converter circuits may be synchronized, such that, for example, sampling of control inputs to the PWM power converter circuits occurs at substantially the same time for each of the PWM power converter circuits. A common phase reference corresponding to an AC voltage phase for the AC load bus may be provided, and the PWM cycles of each of the power converter circuits may synchronized, e.g., phase locked, to the common phase reference. More particularly, the respective PWM cycles of the UPSs may be phase locked to phase locked sinusoidal reference signals generated at each of the UPSs. Sampling for other control functions may also be synchronized to the PWM cycles.

Abstract: A control circuit that activates and deactivates a motor start winding at different motor rpm trip points provides improved accuracy in the trip points by automatically compensating for changes in motor current caused by variations in line voltage and motor winding temperature.

Abstract: A control circuit for an electric motor having start, low speed and high speed windings reactivates the start winding at different reduced motor speeds depending upon whether the motor is running on the low speed winding or the high speed winding. Reactivation of the start winding while the motor is running on the low speed winding automatically deactivates the low speed winding and activates the high speed winding.

Abstract: A control circuit for a two speed electric motor includes high and low speed electronic switches. The high speed electronic switch is biased off when the low speed electronic switch is biased on. The low speed run winding of the motor is activatable only through the low speed electronic switch. The high speed run winding of the motor is activatable either directly through a high speed setting of a speed selector switch or through the high speed electronic switch in a low speed setting of the speed selector switch. Upon activation of the motor start winding, the low speed electronic switch is off and the high speed electronic switch is on.