Patents by Inventor Jason Scott Steill

Jason Scott Steill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • EMBEDDED THIN FILM VARISTOR IN THROUGH GLASS VIAS
    Publication number: 20240113046
    Abstract: Various embodiments disclosed relate to embedded components in glass core layers for semiconductor assemblies. The present disclosure includes a semiconductor assembly with a glass core having one or more cavities and a component embedded into the glass core at the one or more cavities portion, the component at least partially embedded in the glass core, and a semiconductor die attached to the substrate.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Jason Scott Steill, Shayan Kaviani, Srinivas Venkata Ramanuja Pietambaram, Suddhasattwa Nad, Benjamin Duong, Srinivasan Raman, Yi Yang
  • INTEGRATED HORIZONTAL VARISTOR ON GLASS CORE FOR VOLTAGE REGULATION
    Publication number: 20240113048
    Abstract: Various embodiments disclosed relate to embedded components in glass core layers for semiconductor assemblies. The present disclosure includes a semiconductor assembly with a glass core having one or more cavities and a component embedded into the glass core at the one or more cavities portion, the component at least partially embedded in the glass core, and a semiconductor die attached to the substrate.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Srinivasan Raman, Benjamin Duong, Jason Scott Steill, Shayan Kaviani, Srinivas Venkata Ramanuja Pietambaram, Suddhasattwa Nad, Brandon C. Marin, Gang Duan, Yi Yang
  • SUBSTRATE HAVING ONE OR MORE ELECTRICAL INTERCONNECTS
    Publication number: 20240006298
    Abstract: An electronic device may include an integrated circuit, for instance a semiconductor die. The electronic device may include a substrate having a first layer and a second layer. The first and second layers may include interconnects recessed below a surface of the substrate. The substrate may include a passivation layer directly coupled with portions of the interconnects. A solder resist material may at least partially cover portions of the passivation layer directly coupled with the first interconnect surface.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Suddhasattwa Nad, Steve Cho, Marcel Arlan Wall, Onur Ozkan, Ali Lehaf, Yi Yang, Jason Scott Steill, Gang Duan, Brandon C. Marin, Jeremy D. Ecton, Srinivas Venkata Ramanuja Pietambaram, Haifa Hariri, Bai Nie, Hiroki Tanaka, Kyle Mcelhinny, Jason Gamba, Venkata Rajesh Saranam, Kristof Darmawikarta, Haobo Chen