Abstract: An integrated circuit structure and method is capable of automatically tuning the duty cycle of a generated clock signal to any desired value. Tuning of the duty cycle depends upon the precise layout specifications of multiple delay elements of one or more multiplexing circuits of the integrated circuit device. Connecting one or more multiplexing circuits in a serial fashion allows a base frequency to be multiplied in order to produce a generated clock frequency of a desired frequency. Control of select lines to the multiplexing circuits allows the delay path through the one or more multiplexing circuits to be adjusted, thereby automatically adjusting the duty cycle of the generated clock signal.

Abstract: Electro-static-discharge (ESD) protection circuits are supplied for inhibiting the destruction of buffers, drivers, logic and memory cells in Metal-Oxide-Semiconductor (MOS) devices such as a CMOS device including Static-Random-Access-Memory (SRAM). This is accomplished by tiering diodes adjacent the input of the chip and in certain specific areas internally of the chip (e.g. power supplies etc.) providing bidirectional diode protection from over-voltage.

Abstract: Electro-static-discharge (ESD) protection circuits are supplied for inhibiting the destruction of buffers, drivers, logic and memory cells in Metal-Oxide-Semiconductor (MOS) devices such as a CMOS device including Static-Random-Access-Memory (SRAM). This is accomplished by tiering diodes adjacent the input of the chip and in certain specific areas internally of the chip (e.g. power supplies etc.) providing bidirectional diode protection from over-voltage.

Abstract: An integrated circuit preferably includes a plurality of enhancement-mode MOSFETs on a substrate with each MOSFET having an initial threshold voltage, and a plurality of resistors connected to define a resistor voltage divider for passively biasing the MOSFETs to produce an absolute value of an effective threshold voltage of each MOSFET to be lower than an absolute value of the initial threshold voltage. Accordingly, the effective threshold voltages may set to below a predetermined value, and lower supply voltages thereby readily accommodated. For integrated circuits having all n-channel MOSFETs, the threshold voltages are positive, and the voltage divider can be set accordingly. The invention is advantageously also used in CMOS integrated circuits having both p-channel and n-channel MOSFETs. The resistor voltage divider may preferably be set or trimmed after forming the MOSFETs.

Abstract: An integrated circuit having enhanced testing capabilities and a method of testing an integrated circuit are provided. The integrated circuit preferably includes a substrate and a memory block on the substrate. The memory block preferably has a plurality of memory cells arranged in a plurality of rows and a plurality of columns within a defined area on the substrate, at least one bit line connected to each of the plurality of memory cells and defining a column, at least one word line connected to each of the plurality of memory cells and defining a row, and sense amplifying means connected to the at least one bit line for sensing a state of an addressed memory cell in at least one of the plurality of columns. The integrated circuit also includes a selectable stress tester on the substrate and connected to the memory block for selectively stress testing only portions of the memory block and not other portions so as to determine whether to accept or reject a memory block.

Abstract: An integrated circuit includes a plurality of MOSFETs having channels of a first conductivity type, and having active control of an effective threshold voltage of the MOSFETs to be less than an absolute value of an initial threshold voltage. In this embodiment, a first MOSFET has a channel of the first conductivity type, and a second MOSFET is connected to the first MOSFET and has a channel of a second conductivity type. The second MOSFET is preferably biased to a pinch-off region and cooperates with the first MOSFET for generating a control signal related to an effective threshold voltage of the first MOSFET. Moreover, the circuit preferably generates a bias voltage to the plurality of MOSFETs and to the first MOSFET based upon the control signal to set an effective threshold voltage of the plurality of MOSFETs to have an absolute value less than an absolute value of the initial threshold voltage and, more preferably, to a reference voltage. Accordingly, lower supply voltages can be readily accommodated.

Abstract: An integrated circuit includes a plurality of MOSFETs on a substrate. A plurality of sensing MOSFETs are used to generate a plurality of comparison signals based upon comparing signals related to the sensed initial threshold voltages to respective reference voltages from a spread of high to low reference voltage values. The MOSFETs are biased to have a desired effective threshold voltage based upon the plurality of comparison signals. Logic decoding circuits accept the plurality of comparison signals and generate at least one bias control signal. Bias circuits are responsive to the at least one bias control signal for generating a desired bias voltage from among a plurality of bias voltages having a spread of high to low bias voltage values to thereby bias the plurality of MOSFETs to the desired effective threshold voltage. Method aspects of the invention are also disclosed.