Patents by Inventor Jason T. Su
Jason T. Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10925794Abstract: A stationary massage device, system and corresponding methods are used for self-administrated or assisted soft tissue strain release (including trigger point therapy, strain-and-counterstrain therapy and neuromuscular release). The massage device comprises a body, wherein the body may include branches, each having flat surfaces, edges, ridges or corners. The surfaces, edges and ridges may be pushed along the myofilament direction of the soft tissues to produce pressing, rubbing, stretching and pulling actions on the soft tissues as stripping massages. The system can be configured to form different geometric shapes, and made of different materials of different firmness. The system can be further configured to perform unheated, or heated massages; and cooling treatments. In addition to being used alone, the system can be mounted on a piece of wall, a standing frame, furniture or a garment.Type: GrantFiled: July 25, 2017Date of Patent: February 23, 2021Inventor: Jason T. Su
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Publication number: 20190201272Abstract: A stationary massage device, system and corresponding methods are used for self-administrated or assisted soft tissue strain release (including trigger point therapy, strain-and-counterstrain therapy and neuromuscular release). The massage device comprises a body, wherein the body may include branches, each having flat surfaces, edges, ridges or corners. The surfaces, edges and ridges may be pushed along the myofilament direction of the soft tissues to produce pressing, rubbing, stretching and pulling actions on the soft tissues as stripping massages. The system can be configured to form different geometric shapes, and made of different materials of different firmness. The system can be further configured to perform unheated, or heated massages; and cooling treatments. In addition to being used alone, the system can be mounted on a piece of wall, a standing frame, furniture or a garment.Type: ApplicationFiled: March 11, 2019Publication date: July 4, 2019Inventor: Jason T. Su
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Publication number: 20190029908Abstract: Disclosed are stationary massage device, system and methods for self-administrated or assisted soft tissue strain release (including trigger point therapy, strain-and-counterstrain therapy and neuromuscular release). The massage device comprises a body, wherein the body may include branches, each having flat surfaces, edges, ridges or corners. The surfaces, edges and ridges may be pushed along the myofilament direction of the soft tissues to produce pressing, rubbing, stretching and pulling actions on the soft tissues as stripping massages. The system can be configured to form different geometric shapes, and made of different materials of different firmness. The system can be further configured to perform unheated, or heated massages; and cooling treatments. In addition to being used alone, the system can be mounted on a piece of wall, a standing frame, furniture or a garment.Type: ApplicationFiled: July 25, 2017Publication date: January 31, 2019Inventor: Jason T. Su
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Patent number: 9223920Abstract: Aspects of the disclosure provide a circuit, such as an integrated circuit. The circuit includes a first circuit and a second circuit. The second circuit includes a delay circuit configured to cause the second circuit to have substantially matched delay characteristics of the first circuit in response to at least one parameter change of manufacturing, environmental and operational parameters, such as process variation, temperature variation, and supply voltage variation.Type: GrantFiled: March 7, 2014Date of Patent: December 29, 2015Assignee: Marvell World Trade Ltd.Inventors: Jason T. Su, Winston Lee
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Patent number: 9142286Abstract: A device (e.g., an integrated circuit memory device such as a static random access memory device) includes word line drivers. Each of the word line drivers includes a pull-up device that is coupled to a node via a shared line. A precharge device is coupled between a power supply and the node. The precharge device and a pull-up device for a selected word line driver are controlled to allow the power supply to charge the node and then to allow the charge stored in the node to flow into a word line corresponding to the selected word line driver.Type: GrantFiled: April 15, 2013Date of Patent: September 22, 2015Assignee: Applied Micro Circuits CorporationInventors: Jason T Su, Jitendra Khare
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Patent number: 8964452Abstract: Providing for improved write processes of a semiconductor memory are disclosed herein. By way of example, a programmable write assist can be provided that includes partially discharging a supply voltage applied to a memory cell. Partially discharging the supply voltage can improve write speeds to the memory cell, as well as improve reliability of the write process. A write assist circuit can cause the discharging in response to a resistance-modulated signal. Moreover, the resistance-modulated signal can be configured to control an amount or speed of the discharging of the supply voltage. Further, modulation control can be provided to mitigate discharging of the supply voltage beyond a target level, to reduce data loss in a target data cell or an adjacent data cell.Type: GrantFiled: December 26, 2012Date of Patent: February 24, 2015Assignee: Applied Micro Circuits CorporationInventors: Jason T. Su, Bin Liang
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Publication number: 20140307500Abstract: A device (e.g., an integrated circuit memory device such as a static random access memory device) includes word line drivers. Each of the word line drivers includes a pull-up device that is coupled to a node via a shared line. A precharge device is coupled between a power supply and the node. The precharge device and a pull-up device for a selected word line driver are controlled to allow the power supply to charge the node and then to allow the charge stored in the node to flow into a word line corresponding to the selected word line driver.Type: ApplicationFiled: April 15, 2013Publication date: October 16, 2014Applicant: Applied Micro Circuits CorporationInventors: Jason T SU, Jitendra KHARE
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Publication number: 20140218093Abstract: Aspects of the disclosure provide a circuit, such as an integrated circuit. The circuit includes a first circuit and a second circuit. The second circuit includes a delay circuit configured to cause the second circuit to have substantially matched delay characteristics of the first circuit in response to at least one parameter change of manufacturing, environmental and operational parameters, such as process variation, temperature variation, and supply voltage variation.Type: ApplicationFiled: March 7, 2014Publication date: August 7, 2014Applicant: Marvell World Trade Ltd.Inventors: Jason T. SU, Winston Lee
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Publication number: 20140177356Abstract: Providing for improved write processes of a semiconductor memory are disclosed herein. By way of example, a programmable write assist can be provided that includes partially discharging a supply voltage applied to a memory cell. Partially discharging the supply voltage can improve write speeds to the memory cell, as well as improve reliability of the write process. A write assist circuit can cause the discharging in response to a resistance-modulated signal. Moreover, the resistance-modulated signal can be configured to control an amount or speed of the discharging of the supply voltage. Further, modulation control can be provided to mitigate discharging of the supply voltage beyond a target level, to reduce data loss in a target data cell or an adjacent data cell.Type: ApplicationFiled: December 26, 2012Publication date: June 26, 2014Applicant: APPLIED MICRO CIRCUITS CORPORATIONInventors: Jason T. Su, Bin Liang
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Patent number: 8689162Abstract: Aspects of the disclosure provide a circuit, such as an integrated circuit. The circuit includes a first circuit and a second circuit. The second circuit includes a delay circuit configured to cause the second circuit to have substantially matched delay characteristics of the first circuit in response to at least one parameter change of manufacturing, environmental and operational parameters, such as process variation, temperature variation, and supply voltage variation.Type: GrantFiled: September 19, 2011Date of Patent: April 1, 2014Assignee: Marvell World Trade Ltd.Inventors: Jason T. Su, Winston Lee
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Patent number: 8582387Abstract: Described herein are methods and apparatuses for write-assist voltage generation and power-down voltage scaling for static random access memory (SRAM) cells. According to various embodiments, an SRAM cell may include a local power supply voltage node for receiving a power supply voltage generated by a power supply voltage generator circuit, the generated power supply voltage being substantially equal to or less than a global power supply voltage provided to one or more transistors of the SRAM cell during a write-enable or power-down mode.Type: GrantFiled: November 9, 2012Date of Patent: November 12, 2013Assignee: Marvell International Ltd.Inventors: Jason T Su, Karthik Swaminathan
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Patent number: 8526257Abstract: A processor includes an array of memory cells, a control module, a precharge circuit, and an amplifier module. The control module generates a clock signal at a first rate, reduces the first rate to a second rate for a predetermined period, and adjusts the second rate back to the first rate at an end of the predetermined period. The precharge circuit: based on the first rate, precharges first bit lines connected to memory cells in a first row of the array of memory cells; based on the second rate, refrains from precharging the first bit lines; and precharges the first bit lines subsequent to the end of the predetermined period. The amplifier module: based on the first rate, access first instructions stored in the first row; and based on the second rate, accesses second instructions stored in the first row or a second row of the array.Type: GrantFiled: October 22, 2012Date of Patent: September 3, 2013Assignee: Marvell World Trade Ltd.Inventors: Sehat Sutardja, Jason T. Su, Hong-Yi Chen, Jason Sheu, Jensen Tjeng
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Patent number: 8451041Abstract: A flip-flop circuit includes a charge injection module, a sense amp module, and a latch module. The charge injection module is configured to, in response to a clock signal, selectively provide electrical charge from a power supply to a first node. The sense amp module is configured to adjust a voltage of a second node in response to detecting a voltage of the first node crossing a threshold while the charge injection module is providing the electrical charge to the first node. The latch module is configured to in response to the clock signal, store a value based on a voltage of the second node. The latch module is also configured to provide the value as an output of the flip-flop circuit.Type: GrantFiled: July 18, 2011Date of Patent: May 28, 2013Assignee: Marvell World Trade Ltd.Inventors: Jason T. Su, Winston Lee, Yuntian Chen
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Patent number: 8310894Abstract: Described herein are methods and apparatuses for write-assist voltage generation and power-down voltage scaling for static random access memory (SRAM) cells. According to various embodiments, an SRAM cell may include a local power supply voltage node for receiving a power supply voltage generated by a power supply voltage generator circuit, the generated power supply voltage being substantially equal to or less than a global power supply voltage provided to one or more transistors of the SRAM cell during a write-enable or power-down mode.Type: GrantFiled: November 15, 2010Date of Patent: November 13, 2012Assignee: Marvell International Ltd.Inventors: Jason T. Su, Karthik Swaminathan
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Patent number: 8295110Abstract: A processor including a cache memory, a decoder, a precharge circuit, a control module, and an amplifier module. The decoder generates a first word line signal to access first instructions stored in a first word line, and (ii) generates a second word line signal to access second instructions stored in the first word line or a second word line. The precharge circuit (i) precharges first bit lines connected to the first word line prior to accessing each of the first and second instructions. The control module adjusts a rate of a clock signal from a first rate to a second rate. The amplifier module accesses the first instructions based on (i) the first word line signal and (ii) the clock signal at the first rate, and accesses the second instructions based on (i) the second word line signal and (ii) the clock signal at the second rate.Type: GrantFiled: September 26, 2011Date of Patent: October 23, 2012Assignee: Marvell World Trade Ltd.Inventors: Sehat Sutardja, Jason T. Su, Hong-Yi Chen, Jason Sheu, Jensen Tjeng
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Patent number: 8164972Abstract: An address decoder that includes a plurality of predecoders configured to (i) receive and logically combine a clock signal and address signals and (ii) generate addresses and complementary addresses. At least one of the plurality of precoders includes a first logic gate configured to receive the clock signal and one of the address signals, and a second logic gate configured to receive the clock signal and an output of the first logic gate. The address decoder further includes a decoder configured to generate a decoder output based on the addresses and complementary addresses.Type: GrantFiled: December 6, 2010Date of Patent: April 24, 2012Assignee: Marvell International Ltd.Inventor: Jason T. Su
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Publication number: 20120068754Abstract: Aspects of the disclosure provide a circuit, such as an integrated circuit. The circuit includes a first circuit and a second circuit. The second circuit includes a delay circuit configured to cause the second circuit to have substantially matched delay characteristics of the first circuit in response to at least one parameter change of manufacturing, environmental and operational parameters, such as process variation, temperature variation, and supply voltage variation.Type: ApplicationFiled: September 19, 2011Publication date: March 22, 2012Inventors: Jason T. SU, Winston Lee
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Publication number: 20120014196Abstract: A processor including a cache memory, a decoder, a precharge circuit, a control module, and an amplifier module. The decoder generates a first word line signal to access first instructions stored in a first word line, and (ii) generates a second word line signal to access second instructions stored in the first word line or a second word line. The precharge circuit (i) precharges first bit lines connected to the first word line prior to accessing each of the first and second instructions. The control module adjusts a rate of a clock signal from a first rate to a second rate. The amplifier module accesses the first instructions based on (i) the first word line signal and (ii) the clock signal at the first rate, and accesses the second instructions based on (i) the second word line signal and (ii) the clock signal at the second rate.Type: ApplicationFiled: September 26, 2011Publication date: January 19, 2012Inventors: Sehat Sutardja, Jason T. Su, Hong-Yi Chen, Jason Sheu, Jensen Tjeng
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Publication number: 20120013379Abstract: A flip-flop circuit includes a charge injection module, a sense amp module, and a latch module. The charge injection module is configured to, in response to a clock signal, selectively provide electrical charge from a power supply to a first node. The sense amp module is configured to adjust a voltage of a second node in response to detecting a voltage of the first node crossing a threshold while the charge injection module is providing the electrical charge to the first node. The latch module is configured to in response to the clock signal, store a value based on a voltage of the second node. The latch module is also configured to provide the value as an output of the flip-flop circuit.Type: ApplicationFiled: July 18, 2011Publication date: January 19, 2012Inventors: Jason T. Su, Winston Lee, Yuntian Chen
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Patent number: 8089823Abstract: A processor including a memory and a control module. The memory has an array of cells. The control module is configured to: determine a number of access cycles along a first word line; determine an extended period based on the number of the access cycles; generate a word line signal to maintain the first word line in an activated state during (i) an initial period and (ii) the extended period; and access a first cell during the extended period. The first cell is connected to the first word line. The control module is further configured to deactivate the word line and maintain the first word line in a deactivated state while accessing a second cell connected to the first word line. The accessing of the second cell is based on a bit line separation provided during the extended period.Type: GrantFiled: August 25, 2010Date of Patent: January 3, 2012Assignee: Marvell World Trade Ltd.Inventors: Sehat Sutardja, Jason T. Su, Hong-Yi Chen, Jason Sheu, Jensen Tjeng