Patents by Inventor Jason T. Zawodny
Jason T. Zawodny has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20200118603Abstract: The present disclosure includes apparatuses and methods for data transfer between subarrays in memory. An example may include a first subarray of memory cells and a second subarray of memory cells, wherein a first portion of memory cells of the first subarray and a first portion of memory cells of the second subarray are coupled to a first sensing circuitry stripe. A third subarray of memory cells can include a first portion of memory cells coupled to a second sensing circuitry stripe. A second portion of memory cells of the second subarray and a second portion of memory cells of the third subarray can be coupled to a third sensing circuitry stripe. A particular row of the second array can include memory cells from the first portion of memory cells in the second array coupled to memory cells from the second portion of memory cells in the second array.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Jason T. Zawodny, Glen E. Hush, Richard C. Murphy
-
Publication number: 20200051599Abstract: The present disclosure includes apparatuses and methods related to bank coordination in a memory device. A number of embodiments include a method comprising concurrently performing a memory operation by a threshold number of memory regions, and executing a command to cause a budget area to perform a power budget operation associated with the memory operation.Type: ApplicationFiled: October 18, 2019Publication date: February 13, 2020Inventors: Kelley D. Dobelstein, Jason T. Zawodny, Kyle B. Wheeler
-
Patent number: 10522199Abstract: The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that includes an array of memory cells, sensing circuitry, and a memory controller coupled to one another. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A channel controller is configured to receive a block of instructions, the block of instructions including individual instructions for at least one of a gather operation and a scatter operation. The channel controller is configured to send individual instructions to the memory device and to control the memory controller such that the at least one of the gather operation and the scatter operation is executed on the memory device based on a corresponding one of the individual instructions.Type: GrantFiled: August 4, 2017Date of Patent: December 31, 2019Assignee: Micron Technology, Inc.Inventors: Jason T. Zawodny, Kelley D. Dobelstein, Timothy P. Finkbeiner, Richard C. Murphy
-
Patent number: 10510381Abstract: The present disclosure includes apparatuses and methods for data transfer between subarrays in memory. An example may include a first subarray of memory cells and a second subarray of memory cells, wherein a first portion of memory cells of the first subarray and a first portion of memory cells of the second subarray are coupled to a first sensing circuitry stripe. A third subarray of memory cells can include a first portion of memory cells coupled to a second sensing circuitry stripe. A second portion of memory cells of the second subarray and a second portion of memory cells of the third subarray can be coupled to a third sensing circuitry stripe. A particular row of the second array can include memory cells from the first portion of memory cells in the second array coupled to memory cells from the second portion of memory cells in the second array.Type: GrantFiled: September 21, 2018Date of Patent: December 17, 2019Assignee: Micron Technology, Inc.Inventors: Jason T. Zawodny, Glen E. Hush, Richard C. Murphy
-
Publication number: 20190378558Abstract: Apparatuses and methods are provided for reversing data stored in memory. An example apparatus comprises an array of memory cells, a first plurality of sensing components corresponding to a respective first plurality of columns of the array, a second plurality of sensing components corresponding to a respective second plurality of columns of the array, and a plurality of shared input/output (I/O) lines (which may be referred to as SIO lines). Each one of the plurality of SIO lines can be selectively coupled to a respective subset of the first plurality of sensing components and to a respective subset of the second plurality of sensing components. The apparatus can include a controller configured to control reversing a logical sequence of data stored in a group of memory cells coupled to a first access line of the array by performing a plurality of transfer operations via the plurality of SIO lines.Type: ApplicationFiled: August 26, 2019Publication date: December 12, 2019Inventors: Jason T. Zawodny, Glen E. Hush
-
Patent number: 10496286Abstract: The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.Type: GrantFiled: August 4, 2017Date of Patent: December 3, 2019Assignee: Micron Technology, Inc.Inventors: Jason T. Zawodny, Glen E. Hush, Troy A. Manning, Timothy P. Finkbeiner
-
Publication number: 20190362762Abstract: The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that includes an array of memory cells, sensing circuitry, and a memory controller coupled to one another. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A channel controller is configured to receive a block of instructions, the block of instructions including individual instructions for at least one of a gather operation and a scatter operation. The channel controller is configured to send individual instructions to the memory device and to control the memory controller such that the at least one of the gather operation and the scatter operation is executed on the memory device based on a corresponding one of the individual instructions.Type: ApplicationFiled: August 9, 2019Publication date: November 28, 2019Inventors: Jason T. Zawodny, Kelley D. Dobelstein, Timothy P. Finkbeiner, Richard C. Murphy
-
Publication number: 20190355406Abstract: The present disclosure includes apparatuses and methods related to compute components formed over an array of storage elements. An example apparatus comprises a base substrate material and an array of memory cells formed over the base substrate material. The array can include a plurality of access transistors comprising a first semiconductor material. A compute component can be formed over and coupled to the array. The compute component can include a plurality of compute transistors comprising a second semiconductor material. The second semiconductor material can have a higher concentration of doping ions than the first semiconductor material.Type: ApplicationFiled: July 30, 2019Publication date: November 21, 2019Inventor: Jason T. Zawodny
-
Patent number: 10453502Abstract: Apparatuses and methods related to memory bank power coordination in a memory device are disclosed. A method for memory bank power coordination may include concurrently performing a memory operation by a threshold number of memory regions, such as banks or subarrays, and executing a command to cause a power budget operation associated with the memory operation to be performed, based at least in part on information stored in a budget area, such as a register. The threshold number of memory regions may be set based at least in part on a threshold power consumption value, and the number of memory regions to concurrently perform an operation may be controlled by a bank arbiter. A counter having a value representing the threshold number of memory regions may be decremented while performing an operation, or incremented upon completion of an operation, associated with one of the memory regions. A number of the memory regions may be selected to perform a processing-in-memory (PIM) operation.Type: GrantFiled: April 4, 2016Date of Patent: October 22, 2019Assignee: Micron Technology, Inc.Inventors: Kelley D. Dobelstein, Jason T. Zawodny, Kyle B. Wheeler
-
Publication number: 20190286337Abstract: The present disclosure includes apparatuses and methods related to a memory device as the store to pre-resolved instructions. An example apparatus comprises a memory device coupled to a host via a data bus and a control bus. The memory device includes an array of memory cells and sensing circuitry coupled to the array via a plurality of sense lines. The sensing circuitry includes sense amplifiers and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of address translated instructions and/or constant data from the host. The memory controller is configured to write the address translated instructions and/or constant data to a plurality of locations in a bank of the memory device in parallel.Type: ApplicationFiled: June 6, 2019Publication date: September 19, 2019Inventors: Jason T. Zawodny, Glen E. Hush, Troy A. Manning, Timothy P. Finkbeiner
-
Patent number: 10418092Abstract: Apparatuses and methods are provided for reversing data stored in memory. An example apparatus comprises an array of memory cells, a first plurality of sensing components corresponding to a respective first plurality of columns of the array, a second plurality of sensing components corresponding to a respective second plurality of columns of the array, and a plurality of shared input/output (I/O) lines (which may be referred to as SIO lines). Each one of the plurality of SIO lines can be selectively coupled to a respective subset of the first plurality of sensing components and to a respective subset of the second plurality of sensing components. The apparatus can include a controller configured to control reversing a logical sequence of data stored in a group of memory cells coupled to a first access line of the array by performing a plurality of transfer operations via the plurality of SIO lines.Type: GrantFiled: April 24, 2018Date of Patent: September 17, 2019Assignee: Micron Technology, Inc.Inventors: Jason T. Zawodny, Glen E. Hush
-
Patent number: 10373666Abstract: The present disclosure includes apparatuses and methods related to compute components formed over an array of storage elements. An example apparatus comprises a base substrate material and an array of memory cells formed over the base substrate material. The array can include a plurality of access transistors comprising a first semiconductor material. A compute component can be formed over and coupled to the array. The compute component can include a plurality of compute transistors comprising a second semiconductor material. The second semiconductor material can have a higher concentration of doping ions than the first semiconductor material.Type: GrantFiled: November 7, 2017Date of Patent: August 6, 2019Assignee: Micron Technology, Inc.Inventor: Jason T. Zawodny
-
Patent number: 10289542Abstract: The present disclosure includes apparatuses and methods related to a memory device as the store to program instructions. An apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller, coupled to the array and the sensing circuitry is configured to receive a block of instructions including a plurality of program instructions. The memory controller is configured to store the block of instructions in the array and retrieve program instructions to perform logical operations on the compute component.Type: GrantFiled: August 4, 2017Date of Patent: May 14, 2019Assignee: Micron Technology, Inc.Inventors: Jason T. Zawodny, Kyle B. Wheeler, Richard C. Murphy
-
Publication number: 20190121724Abstract: Apparatuses and methods related to a memory device as the store to program instructions are described. An apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller, coupled to the array and the sensing circuitry, is configured to receive a block of instructions including a plurality of program instructions. The memory controller is configured to store the block of instructions in the array and retrieve program instructions to perform logical operations on the compute component.Type: ApplicationFiled: December 18, 2018Publication date: April 25, 2019Inventors: Jason T. Zawodny, Kyle B. Wheeler, Richard C. Murphy
-
Patent number: 10262701Abstract: The present disclosure includes apparatuses and methods for data transfer between subarrays in memory. An example may include a first subarray of memory cells and a second subarray of memory cells, wherein a first portion of memory cells of the first subarray and a first portion of memory cells of the second subarray are coupled to a first sensing circuitry stripe. A third subarray of memory cells can include a first portion of memory cells coupled to a second sensing circuitry stripe. A second portion of memory cells of the second subarray and a second portion of memory cells of the third subarray can be coupled to a third sensing circuitry stripe. A particular row of the second array can include memory cells from the first portion of memory cells in the second array coupled to memory cells from the second portion of memory cells in the second array.Type: GrantFiled: June 7, 2017Date of Patent: April 16, 2019Assignee: Micron Technology, Inc.Inventors: Jason T. Zawodny, Glen E. Hush, Richard C. Murphy
-
Publication number: 20190108863Abstract: The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and one of the plurality of sense lines. The access line can be a same access line as one of the plurality of access lines. The example apparatus comprises a controller configured to cause a corner turn operation on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells to be performed using sensing circuitry.Type: ApplicationFiled: December 10, 2018Publication date: April 11, 2019Inventors: Jason T. Zawodny, Sanjay Tiwari
-
Publication number: 20190034116Abstract: The present disclosure includes apparatuses and methods for data transfer between subarrays in memory. An example may include a first subarray of memory cells and a second subarray of memory cells, wherein a first portion of memory cells of the first subarray and a first portion of memory cells of the second subarray are coupled to a first sensing circuitry stripe. A third subarray of memory cells can include a first portion of memory cells coupled to a second sensing circuitry stripe. A second portion of memory cells of the second subarray and a second portion of memory cells of the third subarray can be coupled to a third sensing circuitry stripe. A particular row of the second array can include memory cells from the first portion of memory cells in the second array coupled to memory cells from the second portion of memory cells in the second array.Type: ApplicationFiled: September 21, 2018Publication date: January 31, 2019Inventors: Jason T. Zawodny, Glen E. Hush, Richard C. Murphy
-
Publication number: 20180357007Abstract: The present disclosure includes apparatuses and methods for data transfer between subarrays in memory. An example may include a first subarray of memory cells and a second subarray of memory cells, wherein a first portion of memory cells of the first subarray and a first portion of memory cells of the second subarray are coupled to a first sensing circuitry stripe. A third subarray of memory cells can include a first portion of memory cells coupled to a second sensing circuitry stripe. A second portion of memory cells of the second subarray and a second portion of memory cells of the third subarray can be coupled to a third sensing circuitry stripe. A particular row of the second array can include memory cells from the first portion of memory cells in the second array coupled to memory cells from the second portion of memory cells in the second array.Type: ApplicationFiled: June 7, 2017Publication date: December 13, 2018Inventors: Jason T. Zawodny, Glen E. Hush, Richard C. Murphy
-
Patent number: 10153008Abstract: The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and one of the plurality of sense lines. The access line can be a same access line as one of the plurality of access lines. The example apparatus comprises a controller configured to cause a corner turn operation on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells to be performed using sensing circuitry.Type: GrantFiled: April 20, 2016Date of Patent: December 11, 2018Assignee: Micron Technology, Inc.Inventors: Jason T. Zawodny, Sanjay Tiwari
-
Publication number: 20180240509Abstract: Apparatuses and methods are provided for reversing data stored in memory. An example apparatus comprises an array of memory cells, a first plurality of sensing components corresponding to a respective first plurality of columns of the array, a second plurality of sensing components corresponding to a respective second plurality of columns of the array, and a plurality of shared input/output (I/O) lines (which may be referred to as SIO lines). Each one of the plurality of SIO lines can be selectively coupled to a respective subset of the first plurality of sensing components and to a respective subset of the second plurality of sensing components. The apparatus can include a controller configured to control reversing a logical sequence of data stored in a group of memory cells coupled to a first access line of the array by performing a plurality of transfer operations via the plurality of SIO lines.Type: ApplicationFiled: April 24, 2018Publication date: August 23, 2018Inventors: Jason T. Zawodny, Glen E. Hush