Abstract: A source-synchronous system is provided in which a master device is configured to vary the phase between a transmitted data signal and a corresponding source-synchronous clock to measure the margins of a data eye at a slave device.

Abstract: Writing to and reading from dynamic random access memory (DRAM) by a system on chip (SoC) over a multiphase multilane memory bus has power consumption optimized based on bit error rate (BER) and one or more thresholds. The bit error rate (BER) may be measured and used to control parameters to achieve optimal balance between power consumption and accuracy. The bit error rate (BER) measurement, purposely adding jitter, and checking against the thresholds is performed during normal mission-mode operation with live traffic. Error detection may cover every memory data transaction that has a block of binary data.

Abstract: A method, an apparatus, and a computer program product for communication within a wireless terminal. The method can be implemented using dedicated logic and managed and controlled by state machines and/or sequencers. Data received or provided in a memory of a first integrated circuit of a terminal is encoded and transmitted in a data packet to a second integrated circuit. A header identifying the data type and providing a destination is included in the data packet. The destination may be identified as a memory address memory of the second integrated circuit that is mapped to a corresponding memory address of the first integrated circuit at which the data is received. In an aspect, the apparatus receives a header, detects an error in the received header, determines a failure to identify a packet boundary when the error is detected, and performs a search operation to identify the packet boundary.

Abstract: Writing to and reading from dynamic random access memory (DRAM) by a system on chip (SoC) over a multiphase multilane memory bus has power consumption optimized based on bit error rate (BER) and one or more thresholds. The bit error rate (BER) may be measured and used to control parameters to achieve optimal balance between power consumption and accuracy. The bit error rate (BER) measurement, purposely adding jitter, and checking against the thresholds is performed during normal mission-mode operation with live traffic. Error detection may cover every memory data transaction that has a block of binary data.

Abstract: A method, an apparatus, and a computer program product for communication within a wireless terminal. The method can be implemented using dedicated logic and managed and controlled by state machines and/or sequencers. Data received or provided in a memory of a first integrated circuit of a terminal is encoded and transmitted in a data packet to a second integrated circuit. A header identifying the data type and providing a destination is included in the data packet. The destination may be identified as a memory address memory of the second integrated circuit that is mapped to a corresponding memory address of the first integrated circuit at which the data is received. In an aspect, the apparatus receives a header, detects an error in the received header, determines a failure to identify a packet boundary when the error is detected, and performs a search operation to identify the packet boundary.

Abstract: An integrated circuit 2 includes a serial data transmitter 12 and a serial data receiver 14. A signal amplitude distorting circuit 30 is provided to introduce distortion in the amplitude of a serial data signal generated by the serial data transmitter 12 and looped back to the serial data receiver 14 so as to stress test the serial data receiver 14.

Abstract: An integrated circuit is provided comprising: a serial transmitter, a serial receiver and a serial connection providing communication between the serial transmitter and the serial receiver. The integrated circuit further comprises a duty cycle distortion circuit so that the integrated circuit can be stress tested by distorting the duty cycle of a signal within the integrated circuit.

Abstract: An integrated circuit 2 is provided with a clamp transistor 20 for providing electrostatic discharge event protection. A detector circuit 28 produces a clamp control signal for switching the clamp transistor 20 to a conductive state so as to provide the electrostatic discharge protection. The detector circuit 28 also generates an electrostatic discharge event signal 36 which is distributed elsewhere within the integrated circuit 2 and controls a protection circuit element 60, 64, 44 to force a processing control signal 40, 52 of a signal processing transistor 38, 54 into a state in which the signal processing transistor 38, 54 is more resistant to electrostatic discharge damage. The signal processing transistors 38, 54 may be P-type field effect transistors associated with a receiver 14 or a transmitter 12 connected to an external signal communication line.

Abstract: An integrated circuit 2 includes a plurality of serial data transmitters 18 and a plurality of serial data receivers 20. On-chip test signal paths 22 with associated on-chip test circuits 24, 26, 28 are provided so as to permit on-chip serial data communication to be performed with test characteristics imposed by the on-chip test circuits 24, 26, 28 thereby providing on-chip stress testing of the data transmitter 18 and the serial data receiver 20.

Abstract: The present invention provides an integrated circuit comprising a serial transmitter, a serial receiver and a serial connection providing communication between the serial transmitter and the serial receiver. The serial transmitter comprises a clock generator and a serializer for serializing data to be transmitted to the serial receiver. A clock control unit coupled to the clock generator alters the clock phase of the clock signal to stress test the serial receiver.

Abstract: An integrated circuit 2 includes a plurality of serial data transmitters 18 and a plurality of serial data receivers 20. On-chip test signal paths 22 with associated on-chip test circuits 24, 26, 28 are provided so as to permit on-chip serial data communication to be performed with test characteristics imposed by the on-chip test circuits 24, 26, 28 thereby providing on-chip stress testing of the data transmitter 18 and the serial data receiver 20.

Abstract: An integrated circuit 2 having a data receiver circuit 14 for a serial data signal also includes a test data generating circuit 24 for self-test purposes. The test generating circuit includes a filter circuit 230, 32, 34, 36 which processes an input test serial data signal to generate an output test serial data signal having enhanced inter-symbol interference for loopback to the data receiver circuit so as to test that data receiver circuit.

Abstract: An integrated circuit 2 is provided with an output driver circuit 12. The output driver circuit 12 one side provides between a first power supply 20 and a second power supply 18 a first transistor 16, a first output 22, a first resistor 14 and, connected in parallel with the first resistor 14, a first bypass transistor 24. The first bypass transistor 24 is controlled by a first bypass control voltage vbp such that as the first output voltage of the first output 22 approaches the second power supply voltage of the second power supply 18, the first bypass transistor 24 serves to bypass the first resistor 14 and provide a single-ended impedance of the output driver circuit 12 which approximates to zero. On the complementary side of the output driver circuit 12 there are similarly provided a second transistor 28, a second resistor 26 and a bypass transistor 32.

Abstract: An integrated circuit 2 includes a serial data transmitter 12 and a serial data receiver 14. A signal amplitude distorting circuit 30 is provided to introduce distortion in the amplitude of a serial data signal generated by the serial data transmitter 12 and looped back to the serial data receiver 14 so as to stress test the serial data receiver 14.

Abstract: An integrated circuit is provided comprising: a serial transmitter, a serial receiver and a serial connection providing communication between the serial transmitter and the serial receiver. The integrated circuit further comprises a duty cycle distortion circuit so that the integrated circuit can be stress tested by distorting the duty cycle of a signal within the integrated circuit.

Abstract: An integrated circuit 2 is provided with a clamp transistor 20 for providing electrostatic discharge event protection. A detector circuit 28 produces a clamp control signal for switching the clamp transistor 20 to a conductive state so as to provide the electrostatic discharge protection. The detector circuit 28 also generates an electrostatic discharge event signal 36 which is distributed elsewhere within the integrated circuit 2 and controls a protection circuit element 60, 64, 44 to force a processing control signal 40, 52 of a signal processing transistor 38, 54 into a state in which the signal processing transistor 38, 54 is more resistant to electrostatic discharge damage. The signal processing transistors 38, 54 may be P-type field effect transistors associated with a receiver 14 or a transmitter 12 connected to an external signal communication line.