Abstract: A memory apparatus includes a mimic redundant device comparator, a reference delay signal generator, and a signal comparison controller. The mimic redundant device comparator is configured to receive an input signal and to delay the input signal according to a mimic delay, so as to generate a comparison signal. The reference delay signal generator is configured to receive the input signal and to delay the input signal according to a plurality of reference delays, so as to generate a plurality of reference delay signals. The signal comparison controller is configured to receive the reference delay signals and the comparison signal. According to a time difference between the comparison signal and the reference delay signals, the signal comparison controller is configured to generate a selected signal and to generate a delay control signal according to the selected signal.

Abstract: A memory apparatus includes a mimic redundant device comparator, a reference delay signal generator, and a signal comparison controller. The mimic redundant device comparator is configured to receive an input signal and to delay the input signal according to a mimic delay, so as to generate a comparison signal. The reference delay signal generator is configured to receive the input signal and to delay the input signal according to a plurality of reference delays, so as to generate a plurality of reference delay signals. The signal comparison controller is configured to receive the reference delay signals and the comparison signal. According to a time difference between the comparison signal and the reference delay signals, the signal comparison controller is configured to generate a selected signal and to generate a delay control signal according to the selected signal.

Abstract: One embodiment provides an electronic system including a delay locked loop and a control circuit. The delay locked loop is configured to be enabled and update lock state data and to be disabled and store the locked state data. The control circuit is configured to periodically enable the delay locked loop in standby mode at an update interval and for an enable period. The control circuit controls the length of the update interval and the length of the enable period to adjust lock state acquisition time for the delay locked loop in exiting the standby mode.

Abstract: One embodiment provides an electronic system including a delay locked loop and a control circuit. The delay locked loop is configured to be enabled and update lock state data and to be disabled and store the locked state data. The control circuit is configured to periodically enable the delay locked loop in standby mode at an update interval and for an enable period. The control circuit controls the length of the update interval and the length of the enable period to adjust lock state acquisition time for the delay locked loop in exiting the standby mode.

Abstract: A method and apparatus for reducing the number of DQ pins and current used to access data in a memory system or data transfer device, wherein an additional bit is temporally encoded on a data word during a singular access cycle. During an access cycle, the pulse level or levels of encoded bits may determine one or more bits values in a data word being expressed, while the pulse/pulses position in time within a data access cycle determines the remaining bits.

Abstract: An oscillator circuit (100) can provide a dual slop temperature response. For a lower temperature range, a capacitor (106) can be charged and/or discharged according to a first current source (302) that provides an essentially constant current source. For a higher temperature range, the capacitor (106) can be charged and/or discharged according to a second current source (304) that can be enabled and/or provide current according to a voltage proportional to absolute temperature. A slightly positive temperature coefficient of a first current source (302) can be offset by a threshold detect circuit (210 and 212) within a second comparator circuit (204) that utilizes the threshold voltage (Vt) of a transistor (212) as a low limit for a capacitor voltage.