Patents by Inventor Jason W. Brandt

Jason W. Brandt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10365988
    Abstract: Embodiments disclosed herein provide for monitoring performance of a processing device to manage non-precise events. A processing device includes a performance counter to track a non-precise event and to increment upon occurrence of the non-precise event, wherein the non-precise event comprises a first type of performance event that is not linked to an instruction in an instruction trace. The processing device also includes a first handler circuit to generate and store a first record, the first record comprising architectural metadata defining a state of the processing device at a time of generation of the first record, wherein the first handler circuit to generate records corresponding to precise events. The processing device further includes a second handler circuit communicably coupled to the first handler circuit, the second handler circuit to cause the first handler circuit to generate a second record for the non-precise event upon overflow of the performance counter.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: July 30, 2019
    Assignee: Intel Corporation
    Inventors: Jonathan D. Combs, Michael W. Chynoweth, Jason W. Brandt, Corey D. Gough
  • Patent number: 10346167
    Abstract: Methods and apparatuses for generating a suppressed address trace are described. In some embodiments, a processor includes a trace generator having a trace suppressor that outputs a suppressed address trace for instructions executed by the processor. In some embodiments, a method to generate a suppressed address trace for a processor includes generating a suppressed address trace of executed instructions from a trace suppressor of a trace generator of the processor.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Toby Opferman, James B. Crossland, Jason W. Brandt, Beeman C. Strong
  • Patent number: 10346280
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for monitoring performance of a processor to manage events. A processor includes a first performance counter to increment upon occurrence of a first type of event in the processor and a second performance counter to increment upon occurrence of a second type of event in the processor. The processor is to reset the second performance counter in response to the first performance counter reaching a first limit.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventor: Jason W. Brandt
  • Publication number: 20190205061
    Abstract: Processor, method, and system for reducing latency in accessing remote registers is described herein. One embodiment of a processor includes one or more remote registers and remote register access circuitry. The remote register access circuitry is to detect a request from the requestor to access a first register of the one or more remote registers, access to the first register in accordance to the request without the requestor having to wait for completion of the access, and provide a notification accessible to the requestor upon completion of the access to the first register of the one or more remote registers.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Eliezer Weissmann, Alexander Gendler, Efraim Rotem, Moshe Cohen, Asit K. Mallick, Jason W. Brandt, Kameswar Subramaniam, Nathan Fellman, Hisham Shafi
  • Patent number: 10327834
    Abstract: A method for manufacturing an end effector assembly includes providing first and second jaw members moveable relative to one another about a pivot between a first, spaced-apart position and a second, approximated position. One of the first and second jaw members includes a cavity defined therein and the other of the first and second jaw members includes a stop member configured to be inserted into the cavity. A gap-setting gauge is grasped between the first and second jaw members to define a gap-distance between the jaw members equivalent to a thickness of the gap-setting gauge. The first and second jaw members are set such that the jaw members are prevented from approximation beyond the gap-distance.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: June 25, 2019
    Assignee: COVIDIEN LP
    Inventors: Joanna Ackley, James D. Allen, IV, Ryan C. Artale, Kim V. Brandt, Dennis W. Butcher, Edward M. Chojin, Gary M. Couture, James S. Cunningham, David M. Garrison, Keir Hart, Russell D. Hempstead, Glenn A. Horner, Daniel A. Joseph, Duane E. Kerr, Dylan R. Kingsley, Peter M. Mueller, Jessica E. C. Olson, Sean T. O'Neill, Jason T. Sanders, Robert M. Sharp, John R. Twomey, Jeffrey R. Unger
  • Patent number: 10313129
    Abstract: A processor of an aspect includes a decode unit to decode a keyed-hash message authentication code instruction. The keyed-hash message authentication code instruction is to indicate a message, to indicate at least one value that is to represent at least one of key information and key indication information, and to indicate a destination storage location. An execution unit is coupled with the decode unit. The execution unit, in response to the keyed-hash message authentication code instruction, is to store a message authentication code corresponding to the message in the destination storage location. The message authentication code is to be consistent with a keyed-hash message authentication code algorithm that is to use a cryptographic hash algorithm. The message authentication code is to be based on a cryptographic key associated with the at least one value. Other processors, methods, systems, and instructions are disclosed.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, Jason W. Brandt
  • Patent number: 10303620
    Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Jason W. Brandt, Sanjoy K. Mondal, Richard A. Uhlig, Gilbert Neiger, Robert T. George
  • Patent number: 10282296
    Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: May 7, 2019
    Assignee: Intel Corporation
    Inventors: Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther, Buford M. Guy, Thomas R. Huff, Elmoustapha Ould-Ahmed-Vall, Bret L. Toll, David Papworth, James D. Allen
  • Patent number: 10275242
    Abstract: An apparatus and method are described for real time instruction tracing. For example, a method according to one embodiment comprises: recording user specified address ranges for which tracing is required; monitoring a next linear instruction pointer (NLIP) values and/or branch linear instruction pointer (BLIP) values to determine if address range has been entered; when the range is entered, compressing the NLIP and/or BLIP values and constructing fixed length packets containing the tracing data; and transferring the fixed length packets to a memory execution cluster.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: April 30, 2019
    Assignee: Intel Corporation
    Inventors: Huy V. Nguyen, Jason W. Brandt, Jonathan J. Tyler
  • Patent number: 10262162
    Abstract: In an embodiment, the present invention includes a processor having an execution logic to execute instructions and a control transfer termination (CTT) logic coupled to the execution logic. This logic is to cause a CTT fault to be raised if a target instruction of a control transfer instruction is not a CTT instruction. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: April 16, 2019
    Assignee: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Jason W. Brandt, Uday Savagaonkar, Ravi L. Sahita
  • Patent number: 10255072
    Abstract: A processor of an aspect includes a decode unit to decode an instruction. The instruction is to explicitly specify a first architectural register and is to implicitly indicate at least a second architectural register. The second architectural register is implicitly to be at a higher register number than the first architectural register. The processor also includes an architectural register replacement unit coupled with the decode unit. The architectural register replacement unit is to replace the first architectural register with a third architectural register, and is to replace the second architectural register with a fourth architectural register. The third architectural register is to be at a lower register number than the first architectural register. The fourth architectural register is to be at a lower register number than the second architectural register. Other processors are also disclosed, as are methods and systems.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: April 9, 2019
    Assignee: Intel Corporation
    Inventors: Mark J. Charney, Robert Valentine, Milind B. Girkar, Ashish Jha, Bret L. Toll, Elmoustapha Ould-Ahmed-Vall, Jesus Corbal San Adrian, Jason W. Brandt
  • Publication number: 20190102323
    Abstract: An embodiment of a semiconductor package apparatus may include technology to identify a first encrypted memory alias corresponding to a first portion of memory based on a verification indicator, where the first portion is decryptable and readable by both a privileged component and an unprivileged component, and identify a second encrypted memory alias corresponding to a second portion of memory based on the verification indicator, where the second portion is accessible by only the unprivileged component. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: David M. Durham, Kai Cong, Vedvyas Shanbhogue, Barry E. Huntley, Jason W. Brandt, Siddhartha Chhabra, Ravi L. Sahita
  • Publication number: 20190041950
    Abstract: In one embodiment, a processor includes one or more cores including a cache memory hierarchy; a performance monitor coupled to the one or more cores, the performance monitor to monitor performance of the one or more cores, the performance monitor to calculate pipeline cost metadata based at least in part on count information associated with the cache memory hierarchy; and a power controller coupled to the performance monitor, the power controller to receive the pipeline cost metadata and determine a low power state for the one or more cores to enter based at least in part on the pipeline cost metadata. Other embodiments are described and claimed.
    Type: Application
    Filed: March 28, 2018
    Publication date: February 7, 2019
    Inventors: Michael W. Chynoweth, Rajshree Chabukswar, Eliezer Weissmann, Jason W. Brandt, Alexander Gendler, Ahmad Yasin, Patrick Konsor, Sneha Gohad, William Freelove
  • Publication number: 20190012266
    Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.
    Type: Application
    Filed: August 28, 2018
    Publication date: January 10, 2019
    Inventors: Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther, Buford M. Guy, Thomas R. Huff, Christopher J. Hughes, Elmoustapha Ould-Ahmed-Vall, Ronak Singhal, Seyed Yahya Sotoudeh, Bret L. Toll, Lihu Rappoport, David Papworth, James D. Allen
  • Patent number: 10175990
    Abstract: According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: January 8, 2019
    Assignee: Intel Corporation
    Inventors: Christopher J. Hughes, Yen-Kuang (Y. K.) Chen, Mayank Bomb, Jason W. Brandt, Mark J. Buxton, Mark J. Charney, Srinivas Chennupaty, Jesus Corbal, Martin G. Dixon, Milind B. Girkar, Jonathan C. Hall, Hideki (Saito) Ido, Peter Lachner, Gilbert Neiger, Chris J. Newburn, Rajesh S. Parthasarathy, Bret L. Toll, Robert Valentine, Jeffrey G. Wiedemeier
  • Publication number: 20180365069
    Abstract: In one embodiment, an apparatus comprises a first processor to generate a first cryptographic key in response to a request from a software application; receive a second cryptographic key generated by a second processor; encrypt the first cryptographic key using the second cryptographic key; and provide the encrypted first cryptographic key for use by the software application.
    Type: Application
    Filed: June 14, 2017
    Publication date: December 20, 2018
    Applicant: Intel Corporation
    Inventors: Daniel Nemiroff, Jason W. Brandt
  • Publication number: 20180357179
    Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.
    Type: Application
    Filed: June 11, 2018
    Publication date: December 13, 2018
    Inventors: Jason W. Brandt, Sanjoy K. Mondal, Richard A. Uhlig, Gilbert Neiger, Robert T. George
  • Patent number: 10142101
    Abstract: Embodiments of an invention for hardware enforced one-way cryptography are disclosed. In one embodiment, a processor includes a processor key location, instruction hardware, and execution hardware. The processor key location is to hold a processor key. The instruction hardware is to receive a first instruction in an instruction set of the processor. The first instruction is to encrypt input data with the processor key and return a handle. The instruction set lacks a second instruction corresponding to the first instruction to decrypt the handle with the processor key to return the input data. The execution hardware is to perform, in response to receipt of the first instruction by the instruction hardware, encryption of the input data with the processor key and to return the handle.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: November 27, 2018
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, Jason W Brandt
  • Patent number: 10114651
    Abstract: According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: October 30, 2018
    Assignee: Intel Corporation
    Inventors: Christopher J. Hughes, Yen-Kuang (Y. K.) Chen, Mayank Bomb, Jason W. Brandt, Mark J. Buxton, Mark J. Charney, Srinivas Chennupaty, Jesus Corbal, Martin G. Dixon, Milind B. Girkar, Jonathan C. Hall, Hideki (Saito) Ido, Peter Lachner, Gilbert Neiger, Chris J. Newburn, Rajesh S. Parthasarathy, Bret L. Toll, Robert Valentine, Jeffrey G. Wiedemeier
  • Patent number: 10097349
    Abstract: Systems and methods for protecting symmetric encryption keys when performing encryption are described. In one embodiment, a computer-implemented method includes retrieving at least one real key from a secure area and executing, with a processor, a key transform instruction to generate at least one transformed key based on receiving the at least one real key. The at least one transformed key is an encrypted version of at least one round key that is encrypted by the processor using the at least one real key. The processor is able to decrypt the at least one transformed key and encrypt the at least one round key.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: October 9, 2018
    Assignee: Intel Corporation
    Inventors: Steven L. Grobman, Jason W. Brandt