Abstract: A serial buffer includes a first port configured to operate in accordance with a first serial protocol and a second port configured to operate in accordance with a second serial protocol. A first translation circuit of the serial buffer allows packets received on the first port to be translated to the second serial protocol, and then transferred to the second port. A second translation circuit of the serial buffer allows packets received on the second port to be translated to the first serial protocol, and then transferred to the first port. Translations may be performed in response to information included in the headers of the received packets, including source ID values, destination ID values and/or case number values.

Abstract: A serial buffer monitors an incoming stream of packets to identify single missing packets and multiple consecutive missing packets. Upon detecting multiple consecutive missing packets, an interrupt is generated, thereby stopping the data transfer. Upon detecting a single missing packet, a single missing packet identifier is inserted into the packet header of the packet that resulted in identification of the single missing packet. The incoming packets, including any inserted single missing packet identifiers, are written to a queue. When the water level reaches the water mark of the queue, the stored packets are read to create an outgoing packet stream. When a packet read from the queue includes an inserted single missing packet identifier, a dummy packet (e.g., a packet having a data payload of all zeros) is inserted into the outgoing packet stream. As a result, real-time applications are capable of processing the outgoing packet stream in a constant fashion.

Abstract: A serial buffer includes a first port configured to implement an serial rapid I/O (sRIO) protocol and a second port configured to implement a Lite-weight serial (Lite) protocol. SRIO packets received on the first port are translated into Lite request packets compatible with the Lite protocol. The Lite request packets are transmitted to the second port. Lite response packets compatible with the Lite protocol are returned to the second port in response to the Lite request packets. The Lite response packets are translated into sRIO response packets compatible with the sRIO protocol. These sRIO response packets are returned to the first port, thereby providing a mechanism to acknowledge successful transmissions from the first port to the second port. Unsuccessful transmissions are identified by a timeout mechanism. The serial buffer also enables transfers from the second port to the first port in a similar manner.

Abstract: In a multi-queue memory system, a plurality of read count pointers (one for each queue) are stored in a read address file, and used to generate empty flags. A read count pointer associated with a first queue is retrieved from the read address file, and it is determined whether the first queue should be available for a re-read operation. If so, the retrieved read count pointer is stored as a first read mark value. The read count pointer is incremented in response to each read operation performed from the first queue, thereby creating an adjusted read count pointer. If a re-read operation is to be performed from the first queue, the first read mark value is stored in the read address file. Otherwise, the adjusted first read count pointer is stored in the read address file. Similar operations are performed on the write side of the multi-queue memory system.

Abstract: A system and method for using a doorbell command to allow sRIO devices to operate as bus masters to retrieve data packets stored in a serial buffer, without requiring the SRIO devices to specify the sizes of the data packets. The serial buffer includes a plurality of queues that store data packets. A doorbell frame request packet identifies the queue to be accessed within the serial buffer, but does not specify the size of the data packet(s) to be retrieved. Upon detecting a doorbell frame request packet, the serial buffer operates as a bus master to transfer the requested data packets out of the selected queue. The selected queue can be configured to operate in a flush mode or a non-flush mode. The serial buffer may also indicate that a received doorbell frame request has attempted to access an empty queue.

Abstract: A multi-port serial buffer having a plurality of queues is configured to include a first set of queues assigned to store write data associated with a first port, and a second set of queues assigned to store write data associated with a second port. The available queues are user-assignable to either the first set or the second set. Write operations to the first set of queues can be performed in parallel with write operations to the second programmable set of queues. In addition, a first predetermined set of queues is assigned to the first port for read operations, and a second predetermined set of queues is assigned to the second port for read operations. Data can be read from the first predetermined set of queues to the first port at the same time that data is read from the second predetermined set of queues to the second port.

Abstract: A serial buffer is configured to transmit a plurality of received data packets through a data packet transfer path to a host processor. A doorbell controller of the serial buffer monitors the number of data packets transmitted to the host processor through the data packet transfer path, and estimates the number of data packets actually received by the host processor. The doorbell controller generates a doorbell command each time that the estimated number of data packets corresponds with a fixed number of data packets in a frame. The doorbell commands are transmitted to the host processor on a doorbell command path, which is faster than the data packet transfer path. The doorbell controller may estimate the number of data packets actually received by the host processor in response to a first delay value, which represents how much faster the doorbell command path is than the data packet transfer path.

Abstract: A serial buffer is provided having a parallel port configured to couple the serial buffer to a first system via a parallel interface protocol. The serial buffer also includes a serial port configured to couple the serial buffer to a second system via a serial interface protocol and control logic that enables data to be transferred between the parallel port and the serial port in an efficient manner. In one embodiment, the parallel interface protocol is substantially identical to a quad-data rate burst of two (QDRII-B2) interface protocol.

Abstract: Status/error reporting is implemented using a doorbell system. A plurality of flag registers are included on a system device, such as a serial buffer. Each flag register has a corresponding address, and stores a plurality of flags. A flag scan controller accesses the flag registers in a predetermined priority order, using the flag register addresses. Upon detecting that one or more of the flags of a flag register are activated, the flag scan controller causes a doorbell command to be generated. The doorbell command includes the flag register address and the corresponding flags. A system processor receives the doorbell command and services the activated flags. Once the activated flags are serviced, the system processor performs one or more software write operations to clear the flags within the system device. The system processor can simultaneously service multiple flags. The system processor can also simultaneously clear multiple flags.

Abstract: On-chip resources of a serial buffer are accessed using priority packets of a Lite-weight protocol. A priority packet path is provided on the serial buffer to support priority packets. Normal data packets are processed on a normal data packet path, which operates in parallel with the priority packet path. The system resources of the serial buffer can be accessed in response to the priority packets, without blocking the flow of normal data packets. Thus, normal data packets may flow through the serial buffer with the maximum bandwidth supported by the serial interface. The Lite-weight protocol also supports read accesses to queues of the serial buffer (which reside on the normal data packet path). The Lite-weight protocol also supports doorbell commands for status/error reporting.

Abstract: A flag logic circuit is provided for use in a multi-queue memory device having a plurality of queues. A first stage memory stores a flag value for each of the queues in the multi-queue memory device. Flag values are routed from the first stage memory to a flag status bus having a width N in the manner described below. A status bus control circuit receives a signal that identifies the number of queues M actually used by the multi-queue memory device, and in response, generates a repeating pattern of X control values, wherein X is equal to (M?(M mod N))/N+1. A selector circuit sequentially routes X sets of N flag values from the first stage memory to the flag status bus in response to the repeating pattern of X control values. The X sets of N flag values include the flag values associated with the queues actually used.

Abstract: A flag logic circuit includes a first comparator configured to generate a first flag value associated with an active read queue of a multi-queue memory device, and a second comparator configured to generate a second flag value associated with an active write queue of the multi-queue memory device. A dual-port memory is adapted to store a flag value for each queue of the multi-queue memory device. The dual-port memory has a first write port configured to receive the first flag value and a second write port configured to receive the second flag value. A first stage storage element is configured to latch each of the flag values stored in the dual-port memory in response to a first clock signal, such that the flag values are synchronized on an active status bus and flag status bus.

Abstract: A write counter provides a write count value synchronized with a write clock signal. A read counter provides a read count value synchronized with a read clock signal. The read and write count values are routed through logic, which introduces noise to these values. A first delay circuit generates a first blanking signal, which has a duration corresponding with the duration of the noise introduced to the write count value, in response to the write clock signal. A second delay circuit generates a second blanking signal, which has a duration corresponding with the duration of the noise introduced to the read count value, in response to the second clock signal. The read and write count values are latched into read and write blanking registers, respectively, in response to the first and second blanking signals, respectively, effectively filtering the introduced noise prior to a subsequently performed comparison operation.

Abstract: A multi-queue memory system includes first and second memory blocks. The first memory block includes a first array of memory cells, a first sense amplifier circuit and a second sense amplifier circuit. The second memory block includes a second array of memory cells, a third sense amplifier circuit and a fourth sense amplifier circuit. Each of the sense amplifier circuits is independently controlled. Each queue of the multi-queue system has entries in both the first and second memory blocks. A first queue is accessed by alternately accessing the first and second arrays via the first and third sense amplifier circuits. A second queue is subsequently accessed by alternately accessing the first and second arrays via the second and fourth sense amplifier circuits.