Patents by Inventor Jasopin Lee

Jasopin Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120112633
    Abstract: A system and method of light bulb and fixture comprising an occupancy sensor, a light meter, and an on/off circuit switch is used to manage the lighting use base on the sensing the presence of people and area lighting condition. The occupancy sensor, light meter, an on-off circuit switch, and a regulator are incorporated into the light bulb or fixture for easy replacement and no need of re-wiring or major fixture change.
    Type: Application
    Filed: November 10, 2010
    Publication date: May 10, 2012
    Inventor: Jasopin Lee
  • Patent number: 6285590
    Abstract: A low power consumption semiconductor memory circuit that includes a memory core (e.g., a ROM core) with a plurality of intersecting bit lines and word lines, as well as a plurality of memory cells at predetermined intersections of the bit and word lines. The low power consumption semiconductor memory circuit also includes a pre-discharge circuit, a multiplexer circuit (MUX), and a sense amplifier circuit. The pre-discharge circuit is electrically connected to the memory core and configured for discharging each of the bit lines to ground (GND). The MUX circuit is electrically connected to the pre-discharge circuit and configured for selecting at least one of the bit lines as its input. Furthermore, the sense amplifier circuit is configured for sensing an electrical state of an output node of the MUX circuit and, in one embodiment, includes a current generator circuit configured to charge a pre-discharged bit line during a READ operation.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: September 4, 2001
    Assignee: National Semiconductor Corporation
    Inventors: Pavel Poplevine, Jasopin Lee, Derek Tao
  • Patent number: 5874754
    Abstract: A microelectronic cell includes a semiconductor substrate, an active area formed in the substrate, a gate formed in the active area, and a first contact formed in the active area. The contact has a width D perpendicular to a reference axis defined in the active area, and is spaced from the reference axis by a minimum spacing E. The gate includes a first section which extends substantially parallel to the reference axis, the first contact being disposed between the first section and said reference axis, the first section being spaced from the first contact by a minimum spacing A; a second section which extends substantially parallel to and is spaced from said reference axis by a minimum spacing C<(A+D+E), the second section being spaced from the first section along said reference axis; and a third section which extends at an angle to the reference axis and joins adjacent ends of the first and second sections.
    Type: Grant
    Filed: March 31, 1995
    Date of Patent: February 23, 1999
    Assignee: LSI Logic Corporation
    Inventors: Jasopin Lee, Gobi Padmanabhan, Abraham Yee, Stanley Yeh