Patents by Inventor Jasvir Singh
Jasvir Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190198986Abstract: A radar support structure includes a vehicle body structure, an emblem, a radar attachment assembly and a radar unit. The vehicle body structure has a front end, with the emblem being attached to the front end of the vehicle body structure. The radar attachment assembly has an attachment portion, a mounting portion and an energy absorbing portion. The energy absorbing portion is disposed between the attachment portion and the mounting portion. The attachment portion is fixedly attached to the front end of the vehicle body structure. The radar unit is installed to the mounting portion such that the radar unit is spaced apart from and aligned with the emblem.Type: ApplicationFiled: December 22, 2017Publication date: June 27, 2019Inventor: Jasvir SINGH
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Patent number: 10027711Abstract: A method and apparatus is provided that includes techniques for providing complete solutions for role-based, rules-driven access enforcement, the techniques including situational awareness and video surveillance. An embodiment addresses blended risk assessment and security across logical systems, IT applications, databases, and physical systems from a single analytic dashboard, with auto-remediation capabilities. Further, an embodiment provides capability and functionality for co-relating seemingly innocent events and activities to detect real threats and risks, while providing powerful alerting and automated remedial action strategies for decisive action.Type: GrantFiled: March 6, 2012Date of Patent: July 17, 2018Assignee: Alert Enterprise, Inc.Inventors: Jasvir Singh Gill, Inderpal Ricky Arora, Srinivasa Kakkera, Subrat Narendra Singh
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Patent number: 10021138Abstract: Techniques are provided that for providing complete solutions for role-based, rules-driven access enforcement, the techniques including active policy enforcement. Techniques address blended risk assessment and security across logical systems, IT applications, databases, physical systems, and operational technology systems in the context of threat and fraud detection, risk analysis and remediation, active policy enforcement and continuous monitoring. Further, techniques provide out of the box workflow rules that give the ability to add, modify, or delete the applicability parameters for policy enforcement.Type: GrantFiled: May 27, 2015Date of Patent: July 10, 2018Assignee: Alert Enterprise, Inc.Inventors: Jasvir Singh Gill, Inderpal Ricky Arora, Srinivasa Kakkera, Subrat Narenda Singh
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Patent number: 10019677Abstract: A method and apparatus is provided that includes techniques for providing complete solutions for role-based, rules-driven active policy enforcement. An embodiment addresses blended risk assessment and security across logical systems, IT applications, databases, physical systems, and operational systems in the context of threat and fraud detection, risk analysis and remediation, compliance checks and continuous monitoring. Further, an embodiment provides ability to embed and enforce active policy enforcement in particular processes.Type: GrantFiled: February 15, 2012Date of Patent: July 10, 2018Assignee: Alert Enterprise, Inc.Inventors: Jasvir Singh Gill, Inderpal Ricky Arora, Srinivasa Kakkera, Madhu Gourineni
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Patent number: 9689924Abstract: An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.Type: GrantFiled: December 28, 2015Date of Patent: June 27, 2017Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Anirudha Kulkarni, Jasvir Singh
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Patent number: 9632140Abstract: An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.Type: GrantFiled: December 18, 2014Date of Patent: April 25, 2017Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Anirudha Kulkarni, Jasvir Singh
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Publication number: 20160131705Abstract: An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.Type: ApplicationFiled: December 28, 2015Publication date: May 12, 2016Inventors: ANIRUDHA KULKARNI, JASVIR SINGH
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Publication number: 20160100362Abstract: The present application is directed to computer-implemented apparatus for controlling a power savings mode characteristic of a device on a network. The apparatus includes a non-transitory memory with instructions for controlling power saving mode characteristic of the device and a processor operably coupled thereto. The processor performs the step of receiving a request to update the characteristics of the device. The processor also performs the step of updating the characteristics of the device based upon the request. The processor further performs the step of sending an acknowledgment that the characteristic has been updated. The application is also directed to a computer-implemented apparatus on a network for supporting buffering and data handling for a power savings mode of a device on the network.Type: ApplicationFiled: September 28, 2015Publication date: April 7, 2016Inventors: SURESH PALANISAMY, MICHAEL F. STARSINIC, QUANG LY, JASVIR SINGH RAMAM, DARSHAN APPAJIGOWDA, NITHYA VIJAY
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Publication number: 20150281287Abstract: Techniques are provided that for providing complete solutions for role-based, rules-driven access enforcement, the techniques including active policy enforcement. Techniques address blended risk assessment and security across logical systems, IT applications, databases, physical systems, and operational technology systems in the context of threat and fraud detection, risk analysis and remediation, active policy enforcement and continuous monitoring. Further, techniques provide out of the box workflow rules that give the ability to add, modify, or delete the applicability parameters for policy enforcement.Type: ApplicationFiled: May 27, 2015Publication date: October 1, 2015Inventors: Jasvir Singh GILL, Inderpal Ricky ARORA, Srinivasa KAKKERA, Subrat Narenda SINGH
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Publication number: 20150106672Abstract: An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.Type: ApplicationFiled: December 18, 2014Publication date: April 16, 2015Inventors: Anirudha Kulkarni, JASVIR SINGH
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Patent number: 8918689Abstract: An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.Type: GrantFiled: August 30, 2010Date of Patent: December 23, 2014Assignee: STMicroelectronics International N.V.Inventors: Anirudha Kulkarni, Jasvir Singh
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Patent number: 8769412Abstract: A method and apparatus provides techniques for providing complete solutions for role-based, rules-driven access enforcement. An embodiment addresses blended risk assessment and security across logical systems, IT applications, databases, and physical systems from a single analytic dashboard, with auto-remediation capabilities. Further, an embodiment provides capability and functionality for providing visual risk and event monitoring, alerting, mitigation, and analytics displayed on a geospatial map.Type: GrantFiled: November 23, 2010Date of Patent: July 1, 2014Assignee: Alert Enterprise, Inc.Inventors: Jasvir Singh Gill, Srinivasa Kakkera, Inderpal Ricky Arora, Ravi Chunduru
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Patent number: 8367543Abstract: A system and method comprises depositing a dielectric layer on a substrate and depositing a metal layer on the dielectric layer. The system and method further includes depositing a high temperature diffusion barrier metal cap on the metal layer. The system and method further includes depositing a second dielectric layer on the high temperature diffusion barrier metal cap and the first dielectric layer, and etching a via into the second dielectric layer, such that the high temperature diffusion barrier metal cap is exposed. The system and method further includes depositing an under bump metallurgy in the via, and forming a C4 ball on the under bump metallurgy layer.Type: GrantFiled: March 21, 2006Date of Patent: February 5, 2013Assignee: International Business Machines CorporationInventors: Mukta Ghate Farooq, Jasvir Singh Jaspal, William Francis Landers, Thomas E. Lombardi, Hai Pham Longworth, H. Bernhard Pogge, Roger A. Quon
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Publication number: 20120224057Abstract: A method and apparatus is provided that includes techniques for providing complete solutions for role-based, rules-driven access enforcement, the techniques including situational awareness and video surveillance. An embodiment addresses blended risk assessment and security across logical systems, IT applications, databases, and physical systems from a single analytic dashboard, with auto-remediation capabilities. Further, an embodiment provides capability and functionality for co-relating seemingly innocent events and activities to detect real threats and risks, while providing powerful alerting and automated remedial action strategies for decisive action.Type: ApplicationFiled: March 6, 2012Publication date: September 6, 2012Inventors: Jasvir Singh GILL, Inderpal Ricky Arora, Srinivasa Kakkera, Subrat Narendra Singh
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Publication number: 20120216243Abstract: A method and apparatus is provided that includes techniques for providing complete solutions for role-based, rules-driven active policy enforcement. An embodiment addresses blended risk assessment and security across logical systems, IT applications, databases, physical systems, and operational systems in the context of threat and fraud detection, risk analysis and remediation, compliance checks and continuous monitoring. Further, an embodiment provides ability to embed and enforce active policy enforcement in particular processes.Type: ApplicationFiled: February 15, 2012Publication date: August 23, 2012Inventors: Jasvir Singh GILL, Inderpal Ricky ARORA, Srinivasa KAKKERA, Madhu GOURINENI
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Publication number: 20120017130Abstract: An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.Type: ApplicationFiled: August 30, 2010Publication date: January 19, 2012Applicant: STMICROELECTRONICS Pvt. Ltd.Inventors: Anirudha KULKARNI, Jasvir Singh
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Publication number: 20110126111Abstract: A method and apparatus provides techniques for providing complete solutions for role-based, rules-driven access enforcement. An embodiment addresses blended risk assessment and security across logical systems, IT applications, databases, and physical systems from a single analytic dashboard, with auto-remediation capabilities. Further, an embodiment provides capability and functionality for providing visual risk and event monitoring, alerting, mitigation, and analytics displayed on a geospatial map.Type: ApplicationFiled: November 23, 2010Publication date: May 26, 2011Inventors: Jasvir Singh GILL, Srinivasa Kakkera, Inderpal Ricky Arora, Ravi Chunduru
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Publication number: 20090320088Abstract: A computer-driven resource manager (122) selectively executes user-initiated tasks (113) according to established rules (112) defining users' permissions for such tasks. A workflow engine (116) manages redefinition of the rules. Responsive to receiving (602) a request to change the rules, the engine processes the request (600). This includes reviewing the request and selecting (604) a corresponding approval path. Also, the workflow engine sequentially proceeds (610, 612, 614, 616, 620) through a sequence of stages defined by the selected path, where in each stage the workflow engine electronically solicits approvals from one or more approvers indicated by the selected approval path. The engine continues through the stages until receiving at least one denial, or all required approvals (616). Responsive to receiving all required approvals, an electronic message is transmitted (618) directing amendment of the rules per the user request.Type: ApplicationFiled: March 30, 2006Publication date: December 24, 2009Inventors: Jasvir Singh Gill, Ravinder Gill, Prasada Rao Pysla, Sandeep K. Malik, Srinivasa Kakkera
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Patent number: 6043305Abstract: Halogen-free, oligomeric or polymeric, alkylene-bridged alkyl phosphonates having the general formula ##STR1## where n is a whole number of from 1 to 20;R.sup.1 and R.sup.5 are each C.sub.1 -C.sub.6 alkyl;R.sup.2 and R.sup.4 are each C.sub.2 -C.sub.10 alkyl andR.sup.3 is C.sub.2 -C.sub.10 alkyl.The use of such phosphonates as, or in connection with, a flame-retardant (e.g. for polyurethane foams, resins and composites, epoxy resins, phenolic resins, paints, varnishes or textiles).Type: GrantFiled: November 10, 1997Date of Patent: March 28, 2000Assignee: Albright & Wilson UK LimitedInventors: Christopher John Harris, Gary Woodward, Andrew John Taylor, Jasvir Singh Manku