Patents by Inventor Jasvir Singh

Jasvir Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10019677
    Abstract: A method and apparatus is provided that includes techniques for providing complete solutions for role-based, rules-driven active policy enforcement. An embodiment addresses blended risk assessment and security across logical systems, IT applications, databases, physical systems, and operational systems in the context of threat and fraud detection, risk analysis and remediation, compliance checks and continuous monitoring. Further, an embodiment provides ability to embed and enforce active policy enforcement in particular processes.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: July 10, 2018
    Assignee: Alert Enterprise, Inc.
    Inventors: Jasvir Singh Gill, Inderpal Ricky Arora, Srinivasa Kakkera, Madhu Gourineni
  • Patent number: 10021138
    Abstract: Techniques are provided that for providing complete solutions for role-based, rules-driven access enforcement, the techniques including active policy enforcement. Techniques address blended risk assessment and security across logical systems, IT applications, databases, physical systems, and operational technology systems in the context of threat and fraud detection, risk analysis and remediation, active policy enforcement and continuous monitoring. Further, techniques provide out of the box workflow rules that give the ability to add, modify, or delete the applicability parameters for policy enforcement.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: July 10, 2018
    Assignee: Alert Enterprise, Inc.
    Inventors: Jasvir Singh Gill, Inderpal Ricky Arora, Srinivasa Kakkera, Subrat Narenda Singh
  • Patent number: 9689924
    Abstract: An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: June 27, 2017
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Anirudha Kulkarni, Jasvir Singh
  • Patent number: 9632140
    Abstract: An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: April 25, 2017
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Anirudha Kulkarni, Jasvir Singh
  • Publication number: 20160131705
    Abstract: An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.
    Type: Application
    Filed: December 28, 2015
    Publication date: May 12, 2016
    Inventors: ANIRUDHA KULKARNI, JASVIR SINGH
  • Publication number: 20160100362
    Abstract: The present application is directed to computer-implemented apparatus for controlling a power savings mode characteristic of a device on a network. The apparatus includes a non-transitory memory with instructions for controlling power saving mode characteristic of the device and a processor operably coupled thereto. The processor performs the step of receiving a request to update the characteristics of the device. The processor also performs the step of updating the characteristics of the device based upon the request. The processor further performs the step of sending an acknowledgment that the characteristic has been updated. The application is also directed to a computer-implemented apparatus on a network for supporting buffering and data handling for a power savings mode of a device on the network.
    Type: Application
    Filed: September 28, 2015
    Publication date: April 7, 2016
    Inventors: SURESH PALANISAMY, MICHAEL F. STARSINIC, QUANG LY, JASVIR SINGH RAMAM, DARSHAN APPAJIGOWDA, NITHYA VIJAY
  • Publication number: 20150281287
    Abstract: Techniques are provided that for providing complete solutions for role-based, rules-driven access enforcement, the techniques including active policy enforcement. Techniques address blended risk assessment and security across logical systems, IT applications, databases, physical systems, and operational technology systems in the context of threat and fraud detection, risk analysis and remediation, active policy enforcement and continuous monitoring. Further, techniques provide out of the box workflow rules that give the ability to add, modify, or delete the applicability parameters for policy enforcement.
    Type: Application
    Filed: May 27, 2015
    Publication date: October 1, 2015
    Inventors: Jasvir Singh GILL, Inderpal Ricky ARORA, Srinivasa KAKKERA, Subrat Narenda SINGH
  • Publication number: 20150106672
    Abstract: An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.
    Type: Application
    Filed: December 18, 2014
    Publication date: April 16, 2015
    Inventors: Anirudha Kulkarni, JASVIR SINGH
  • Patent number: 8918689
    Abstract: An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: December 23, 2014
    Assignee: STMicroelectronics International N.V.
    Inventors: Anirudha Kulkarni, Jasvir Singh
  • Patent number: 8769412
    Abstract: A method and apparatus provides techniques for providing complete solutions for role-based, rules-driven access enforcement. An embodiment addresses blended risk assessment and security across logical systems, IT applications, databases, and physical systems from a single analytic dashboard, with auto-remediation capabilities. Further, an embodiment provides capability and functionality for providing visual risk and event monitoring, alerting, mitigation, and analytics displayed on a geospatial map.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: July 1, 2014
    Assignee: Alert Enterprise, Inc.
    Inventors: Jasvir Singh Gill, Srinivasa Kakkera, Inderpal Ricky Arora, Ravi Chunduru
  • Patent number: 8367543
    Abstract: A system and method comprises depositing a dielectric layer on a substrate and depositing a metal layer on the dielectric layer. The system and method further includes depositing a high temperature diffusion barrier metal cap on the metal layer. The system and method further includes depositing a second dielectric layer on the high temperature diffusion barrier metal cap and the first dielectric layer, and etching a via into the second dielectric layer, such that the high temperature diffusion barrier metal cap is exposed. The system and method further includes depositing an under bump metallurgy in the via, and forming a C4 ball on the under bump metallurgy layer.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: February 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Mukta Ghate Farooq, Jasvir Singh Jaspal, William Francis Landers, Thomas E. Lombardi, Hai Pham Longworth, H. Bernhard Pogge, Roger A. Quon
  • Publication number: 20120224057
    Abstract: A method and apparatus is provided that includes techniques for providing complete solutions for role-based, rules-driven access enforcement, the techniques including situational awareness and video surveillance. An embodiment addresses blended risk assessment and security across logical systems, IT applications, databases, and physical systems from a single analytic dashboard, with auto-remediation capabilities. Further, an embodiment provides capability and functionality for co-relating seemingly innocent events and activities to detect real threats and risks, while providing powerful alerting and automated remedial action strategies for decisive action.
    Type: Application
    Filed: March 6, 2012
    Publication date: September 6, 2012
    Inventors: Jasvir Singh GILL, Inderpal Ricky Arora, Srinivasa Kakkera, Subrat Narendra Singh
  • Publication number: 20120216243
    Abstract: A method and apparatus is provided that includes techniques for providing complete solutions for role-based, rules-driven active policy enforcement. An embodiment addresses blended risk assessment and security across logical systems, IT applications, databases, physical systems, and operational systems in the context of threat and fraud detection, risk analysis and remediation, compliance checks and continuous monitoring. Further, an embodiment provides ability to embed and enforce active policy enforcement in particular processes.
    Type: Application
    Filed: February 15, 2012
    Publication date: August 23, 2012
    Inventors: Jasvir Singh GILL, Inderpal Ricky ARORA, Srinivasa KAKKERA, Madhu GOURINENI
  • Publication number: 20120017130
    Abstract: An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.
    Type: Application
    Filed: August 30, 2010
    Publication date: January 19, 2012
    Applicant: STMICROELECTRONICS Pvt. Ltd.
    Inventors: Anirudha KULKARNI, Jasvir Singh
  • Publication number: 20110126111
    Abstract: A method and apparatus provides techniques for providing complete solutions for role-based, rules-driven access enforcement. An embodiment addresses blended risk assessment and security across logical systems, IT applications, databases, and physical systems from a single analytic dashboard, with auto-remediation capabilities. Further, an embodiment provides capability and functionality for providing visual risk and event monitoring, alerting, mitigation, and analytics displayed on a geospatial map.
    Type: Application
    Filed: November 23, 2010
    Publication date: May 26, 2011
    Inventors: Jasvir Singh GILL, Srinivasa Kakkera, Inderpal Ricky Arora, Ravi Chunduru
  • Publication number: 20090320088
    Abstract: A computer-driven resource manager (122) selectively executes user-initiated tasks (113) according to established rules (112) defining users' permissions for such tasks. A workflow engine (116) manages redefinition of the rules. Responsive to receiving (602) a request to change the rules, the engine processes the request (600). This includes reviewing the request and selecting (604) a corresponding approval path. Also, the workflow engine sequentially proceeds (610, 612, 614, 616, 620) through a sequence of stages defined by the selected path, where in each stage the workflow engine electronically solicits approvals from one or more approvers indicated by the selected approval path. The engine continues through the stages until receiving at least one denial, or all required approvals (616). Responsive to receiving all required approvals, an electronic message is transmitted (618) directing amendment of the rules per the user request.
    Type: Application
    Filed: March 30, 2006
    Publication date: December 24, 2009
    Inventors: Jasvir Singh Gill, Ravinder Gill, Prasada Rao Pysla, Sandeep K. Malik, Srinivasa Kakkera
  • Patent number: 6043305
    Abstract: Halogen-free, oligomeric or polymeric, alkylene-bridged alkyl phosphonates having the general formula ##STR1## where n is a whole number of from 1 to 20;R.sup.1 and R.sup.5 are each C.sub.1 -C.sub.6 alkyl;R.sup.2 and R.sup.4 are each C.sub.2 -C.sub.10 alkyl andR.sup.3 is C.sub.2 -C.sub.10 alkyl.The use of such phosphonates as, or in connection with, a flame-retardant (e.g. for polyurethane foams, resins and composites, epoxy resins, phenolic resins, paints, varnishes or textiles).
    Type: Grant
    Filed: November 10, 1997
    Date of Patent: March 28, 2000
    Assignee: Albright & Wilson UK Limited
    Inventors: Christopher John Harris, Gary Woodward, Andrew John Taylor, Jasvir Singh Manku