Abstract: A circuit including a memory cell, a pair of bit lines, a precharge circuit, a multiplexer, and a pull-up circuit is provided herein. The bit lines are coupled to the memory cell. The precharge circuit is coupled between the bit lines and configured to precharge each of the bit lines to approximately a first supply voltage to begin the write operation. The multiplexer is configured to select which bit line is a zero bit driven to a low logic level during the write operation and after the precharge circuit is turned off. After the write operation begins, the pull-up circuit is coupled to the bit lines and configured to select which bit line is a non-zero bit line driven to a high logic level.