Abstract: A first type of prediction, for controlling execution of at least one instruction by processing circuitry, is based at least on a first prediction table storing prediction information looked up based on at least a first portion of branch history information stored in branch history storage corresponding to a first predetermined number of branches. In response to detecting an execution state switch of the processing circuitry from a first execution state to a second, more privileged, execution state, use of the first prediction table for determining the first type of prediction is disabled. In response to detecting that a number of branches causing an update to the branch history storage since the execution state switch is greater than or equal to the first predetermined number, use of the first prediction table in determining the first type of prediction is re-enabled.

Abstract: A first type of prediction, for controlling execution of at least one instruction by processing circuitry, is based at least on a first prediction table storing prediction information looked up based on at least a first portion of branch history information stored in branch history storage corresponding to a first predetermined number of branches. In response to detecting an execution state switch of the processing circuitry from a first execution state to a second, more privileged, execution state, use of the first prediction table for determining the first type of prediction is disabled. In response to detecting that a number of branches causing an update to the branch history storage since the execution state switch is greater than or equal to the first predetermined number, use of the first prediction table in determining the first type of prediction is re-enabled.

Abstract: Aspects of the present disclosure relate to an apparatus comprising fetch circuitry. The fetch circuitry comprises a pointer-based fetch queue for queuing processing instructions retrieved from a storage, and pointer storage for storing a pointer identifying a current fetch queue element. The apparatus comprises decode circuitry having a plurality of decode units, and fetch queue extraction circuitry to, based on the pointer, extract the content of a plurality of elements of the fetch queue; apply combinatorial logic to speculatively produce, from the content of said fetch queue entries, a plurality of speculative potential instructions; and transmit each speculative potential instruction to a corresponding one of said decode units. Each decode unit is configured to decode the corresponding speculative potential instruction.

Abstract: Aspects of the present disclosure relate to an apparatus comprising fetch circuitry. The fetch circuitry comprises a pointer-based fetch queue for queuing processing instructions retrieved from a storage, and pointer storage for storing a pointer identifying a current fetch queue element. The apparatus comprises decode circuitry having a plurality of decode units, and fetch queue extraction circuitry to, based on the pointer, extract the content of a plurality of elements of the fetch queue; apply combinatorial logic to speculatively produce, from the content of said fetch queue entries, a plurality of speculative potential instructions; and transmit each speculative potential instruction to a corresponding one of said decode units. Each decode unit is configured to decode the corresponding speculative potential instruction.

Abstract: A processing system 2 includes a processing pipeline 12, 14, 16, 18, 28 which includes fetch circuitry 12 for fetching instructions to be executed from a memory 6, 8. Buffer control circuitry 34 is responsive to a programmable trigger, such as explicit hint instructions delimiting an instruction burst, or predetermined configuration data specifying parameters of a burst together with a synchronising instruction, to trigger the buffer control circuitry to stall a stallable portion of the processing pipeline (e.g. issue circuitry 16), to accumulate within one or more buffers 30, 32 fetched instructions starting from a predetermined starting instruction, and, when those instructions have been accumulated, to restart the stallable portion of the pipeline.

Abstract: A processing system 2 includes a processing pipeline 12, 14, 16, 18, 28 which includes fetch circuitry 12 for fetching instructions to be executed from a memory 6, 8. Buffer control circuitry 34 is responsive to a programmable trigger, such as explicit hint instructions delimiting an instruction burst, or predetermined configuration data specifying parameters of a burst together with a synchronising instruction, to trigger the buffer control circuitry to stall a stallable portion of the processing pipeline (e.g. issue circuitry 16), to accumulate within one or more buffers 30, 32 fetched instructions starting from a predetermined starting instruction, and, when those instructions have been accumulated, to restart the stallable portion of the pipeline.

Abstract: A processing system includes a processing pipeline which includes fetch circuitry for fetching instructions to be executed from a memory. Buffer control circuitry is responsive to a programmable trigger, such as explicit hint instructions delimiting an instruction burst, or predetermined configuration data specifying parameters of a burst together with a synchronising instruction, to trigger the buffer control circuitry to stall a stallable portion of the processing pipeline (e.g. issue circuitry), to accumulate within one or more buffers fetched instructions starting from a predetermined starting instruction, and, when those instructions have been accumulated, to restart the stallable portion of the pipeline.

Abstract: Embodiments include a method for verifying a counter design within a tolerance window within which a race condition occurs between a context event and a design event. The method includes receiving a plurality of events within the counter design, the plurality of events including the context event and the design event. The method also includes dynamically determining the tolerance window around the context event by setting a first portion of the tolerance window to precede an occurrence of the context event and by setting a second portion of the tolerance window to follow the context event. Additionally, the method includes performing a verification of whether the design event is within the first portion of the tolerance window or the second portion of the tolerance window.

Abstract: A processing system 2 includes a processing pipeline 12, 14, 16, 18, 28 which includes fetch circuitry 12 for fetching instructions to be executed from a memory 6, 8. Buffer control circuitry 34 is responsive to a programmable trigger, such as explicit hint instructions delimiting an instruction burst, or predetermined configuration data specifying parameters of a burst together with a synchronising instruction, to trigger the buffer control circuitry to stall a stallable portion of the processing pipeline (e.g. issue circuitry 16), to accumulate within one or more buffers 30, 32 fetched instructions starting from a predetermined starting instruction, and, when those instructions have been accumulated, to restart the stallable portion of the pipeline.

Abstract: Embodiments include a method for verifying a counter design within a tolerance window within which a race condition occurs between a context event and a design event. The method includes receiving a plurality of events within the counter design, the plurality of events including the context event and the design event. The method also includes dynamically determining the tolerance window around the context event by setting a first portion of the tolerance window to precede an occurrence of the context event and by setting a second portion of the tolerance window to follow the context event. Additionally, the method includes performing a verification of whether the design event is within the first portion of the tolerance window or the second portion of the tolerance window.

Abstract: A method comprises identifying a number of branches (Nb) and a number of iterations (Ni) in a loop in an instruction stream, generating a number of forward branches until the number of forward branches equals Nb, generating a non-branch instruction in between the forward branch instruction, recording in a memory, instruction stream generated and a history of each branch, an associated target address of each branch, and whether the branch is a taken branch or a not taken branch, determining whether a loop iterator number (i) is less than Ni?1, generating a backward branch with a target address which is greater than or equal to the start address and is lesser than the current address responsive to determining that (i) is less than Ni, and recording in the memory, a branch instruction of the generated backward branch and the associated target address of the backward branch.

Abstract: Embodiments include a method for verifying a counter design within a tolerance window within which a race condition occurs between a context event and a design event. The method includes receiving a plurality of events within the counter design, the plurality of events including the context event and the design event. The method also includes dynamically determining the tolerance window around the context event by setting a first portion of the tolerance window to precede an occurrence of the context event and by setting a second portion of the tolerance window to follow the context event. Additionally, the method includes performing a verification of whether the design event is within the first portion of the tolerance window or the second portion of the tolerance window.

Abstract: Embodiments relate to testing memory write operations. An aspect includes detecting a first write operation to a set of “n” divisions in a memory table, and defining a selected set of entries of an optimization checking table corresponding to the set of “n” divisions of the memory table. The aspect includes determining that at least one selected entry of the selected set of entries is not among an optimal set of entries of the checking table. The aspect further includes determining whether to generate an optimization error or to end an optimization analysis of the first write operation without generating the optimization error by comparing the first time stamps of one or both of the at least one selected entry and one or more optimal entries of the optimal set of entries to a temporal window defined by a predetermined duration.

Abstract: A method comprises identifying a number of branches (Nb) and a number of iterations (Ni) in a loop in an instruction stream, generating a number of forward branches until the number of forward branches equals Nb, generating a non-branch instruction in between the forward branch instruction, recording in a memory, instruction stream generated and a history of each branch, an associated target address of each branch, and whether the branch is a taken branch or a not taken branch, determining whether a loop iterator number (i) is less than Ni?1, generating a backward branch with a target address which is greater than or equal to the start address and is lesser than the current address responsive to determining that (i) is less than Ni, and recording in the memory, a branch instruction of the generated backward branch and the associated target address of the backward branch.

Abstract: Embodiments include a method, system, and computer program product for verifying a counter design. A method includes receiving a plurality of events within the counter design. The plurality of events can include a context event and a design event. The method also includes determining a tolerance window in response to the receiving of the context. The tolerance window is defined around the context event and includes a first portion before an occurrence of the context event and a second portion after the context event. The method further includes performing a verification algorithm to identify whether the design event is within the tolerance window and should be accounted for by a design model counter of the counter design.

Abstract: Embodiments include a method for verifying a counter design within a tolerance window within which a race condition occurs between a context event and a design event. The method includes receiving a plurality of events within the counter design, the plurality of events including the context event and the design event. The method also includes dynamically determining the tolerance window around the context event by setting a first portion of the tolerance window to precede an occurrence of the context event and by setting a second portion of the tolerance window to follow the context event. Additionally, the method includes performing a verification of whether the design event is within the first portion of the tolerance window or the second portion of the tolerance window.

Abstract: Technical solutions are described for dynamically managing an operand-store-compare (OSC) prediction table for load and store operations executed out-of-order. One general aspect includes a method that includes receiving a request to retire a queue entry corresponding to an instruction. The method also includes identifying an OSC prediction for the instruction based on an OSC prediction table entry, where the OSC prediction indicates if the instruction is predicted to hit an OSC hazard. The method also includes determining if the instruction hit the OSC hazard. The method also includes in response to the OSC prediction indicating that the instruction is predicted to hit the OSC hazard and the instruction not hitting the OSC hazard, invalidating the OSC prediction table entry corresponding to the instruction. The present document further describes examples of other aspects such as methods, computer products.

Abstract: Technical solutions are described for dynamically managing an operand-store-compare (OSC) prediction table for load and store operations executed out-of-order. One general aspect includes a method that includes receiving a request to retire a queue entry corresponding to an instruction. The method also includes identifying an OSC prediction for the instruction based on an OSC prediction table entry, where the OSC prediction indicates if the instruction is predicted to hit an OSC hazard. The method also includes determining if the instruction hit the OSC hazard. The method also includes in response to the OSC prediction indicating that the instruction is predicted to hit the OSC hazard and the instruction not hitting the OSC hazard, invalidating the OSC prediction table entry corresponding to the instruction. The present document further describes examples of other aspects such as methods, computer products.

Abstract: A method comprises identifying a number of branches (Nb) and a number of iterations (Ni) in a loop in an instruction stream, generating a number of forward branches until the number of forward branches equals Nb, generating a non-branch instruction in between the forward branch instruction, recording in a memory, instruction stream generated and a history of each branch, an associated target address of each branch, and whether the branch is a taken branch or a not taken branch, determining whether a loop iterator number (i) is less than Ni?1, generating a backward branch with a target address which is greater than or equal to the start address and is lesser than the current address responsive to determining that (i) is less than Ni, and recording in the memory, a branch instruction of the generated backward branch and the associated target address of the backward branch.

Abstract: Technical solutions are described for dynamically managing an operand-store-compare (OSC) prediction table for load and store operations executed out-of-order. One general aspect includes a method that includes receiving a request to retire a queue entry corresponding to an instruction. The method also includes identifying an OSC prediction for the instruction based on an OSC prediction table entry, where the OSC prediction indicates if the instruction is predicted to hit an OSC hazard. The method also includes determining if the instruction hit the OSC hazard. The method also includes in response to the OSC prediction indicating that the instruction is predicted to hit the OSC hazard and the instruction not hitting the OSC hazard, invalidating the OSC prediction table entry corresponding to the instruction. The present document further describes examples of other aspects such as methods, computer products.