Patents by Inventor Jatin Chhugani

Jatin Chhugani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150130795
    Abstract: Techniques for three-dimensional garment simulation using parallel computing are presented herein. An access module can be configured to access a three-dimensional garment model of a garment. The garment model can include garment points that represent a surface of the garment. A processor, having a plurality of cores, can be configured by a garment simulation module to calculate one or more exerted forces on a subset of garment points. Additionally, the garment simulation module can generate cross pairs and apportion the generated cross pairs among the plurality of cores. Moreover, the garment simulation module can determine, using the plurality of vector execution units in parallel based on an organized data layout, whether boundaries of the first subgroup of cross pairs are overlapping based on the one or more exerted forces. Subsequently, the garment simulation module can calculate one or more simulated forces acting on the garment points based on the determination.
    Type: Application
    Filed: October 31, 2014
    Publication date: May 14, 2015
    Inventors: Jatin Chhugani, Jonathan Su, Mihir Naware
  • Publication number: 20150134494
    Abstract: Techniques for extraction of body parameters, dimensions and shape of a customer are presented herein. A model descriptive of a garment, a corresponding calibration factor and reference garment shapes can be assessed. A garment shape corresponding to the three-dimensional model can be selected from the reference garment shapes based on a comparison of the three-dimensional model with the reference garment shapes. A reference feature from the plurality of reference features may be associated with the model feature. A measurement of the reference feature may be calculated based on the association and the calibration factor. The computed measurement can be stored in a body profile associated with a user. An avatar can be generated for the user based on the body profile and be used to show or indicate fit of a garment, as well as make fit and size recommendations.
    Type: Application
    Filed: August 29, 2014
    Publication date: May 14, 2015
    Inventors: Jonathan Su, Mihir Naware, Jatin Chhugani
  • Publication number: 20150134493
    Abstract: Techniques for three-dimensional garment simulation are presented herein. An access module can be configured to access a three-dimensional garment model of a garment. The garment model can include garment points that represent a surface of the garment. Additionally, a three-dimensional body model can be generated based on body measurements, body scanning, or garment information. A processor can be configured by a garment module to position at least a portion of the generated three-dimensional body model inside the garment points, and calculate one or more simulated forces acting on a subset of the garment points. Moreover, a rendering module can be configured to generate an image of the three-dimensional garment model draped on the three-dimensional body model based on the calculated one or more simulated forces. Furthermore, a display module can be configured to present the generated image on a display of a device.
    Type: Application
    Filed: July 31, 2014
    Publication date: May 14, 2015
    Inventors: Jonathan Su, Mihir Naware, Jatin Chhugani
  • Publication number: 20150134495
    Abstract: Techniques for an omni-channel approach for displaying simulated digital apparel content are presented herein. A machine can detect an available amount of a computing resource on a client device. A determination that the client device is to render only a three-dimensional body model, among a set of models that includes the three-dimensional body model and a three-dimensional garment model, and that a server is to render the three-dimensional garment model, may occur based on the detected available amount of the computing resource on the client device. The machine can provide the client device with the three-dimensional garment model draped on the three-dimensional body model. The machine can cause the server to render at least a portion of the three-dimensional garment model in accordance with the determination. The machine can cause the client device to render at least a portion of the three-dimensional body model in accordance with the determination.
    Type: Application
    Filed: September 30, 2014
    Publication date: May 14, 2015
    Inventors: Mihir Naware, Jatin Chhugani, Jonathan Su
  • Publication number: 20150134302
    Abstract: Techniques for generating and presenting a three-dimensional garment model are presented herein. A communication interface can be configured to receive images, where all visible parts of the garment may be captured by the received images. A garment creation module can be configured to generate partial shapes of the garment based on the received images. Additionally, the garment creation module can determine a type of garment by comparing the generated partial shapes to a database of reference garment shapes. Furthermore, the garment creation module can generate a three-dimensional garment model by joining the partial shapes based on the determined type of garment, and can tessellate the generated three-dimensional garment model. A user interface can be configured to present the tessellated three-dimensional garment model on a three-dimensional body model.
    Type: Application
    Filed: May 5, 2014
    Publication date: May 14, 2015
    Inventors: Jatin Chhugani, Jonathan Su, Mihir Naware
  • Publication number: 20140176590
    Abstract: A texture unit may be used to perform general purpose mathematical computations such as dot products. This enables some general purpose computations and operations to be offloaded from a central processing unit to the texture unit. The texture unit may use linear interpolators in order to perform the dot product calculations.
    Type: Application
    Filed: October 16, 2013
    Publication date: June 26, 2014
    Inventors: Victor W. Lee, Mikhail Smelyanskiy, Ganesh S. Dasika, Jose Gonzalez, Jatin Chhugani, Yen-Kuang Chen, Changkyu Kim, Julio Gago, Santiago Galan, Victor Moya Del Barrio
  • Patent number: 8743114
    Abstract: Methods and systems to determine view cell occlusion, including to project objects of a 3-dimensional graphics environment to a 2-dimensional image plane with respect to the view point, to reduce sizes of corresponding object images, to generate an occluder map from the reduced-size object images, to compare at least a portion of the object images to the occluder map, and to identify an object as occluded with respect to the view cell when pixel depth values of the object image are greater than corresponding pixel depth values of the occluder map. Methods and systems to reduce an object image size include methods and systems to nullify pixel depth values within a radius of an edge pixel, and to determine the radius as a distance from the edge pixel to a second pixel so that a line between the view point and the second pixel is parallel with one or more of a line and a plane that is tangential to a sphere enclosing the view cell and a point on the object that corresponds to the edge pixel.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: June 3, 2014
    Assignee: Intel Corporation
    Inventors: Changkyu Kim, Jatin Chhugani, Christian Bienia, Daehyun Kim, Anthony Ngueyn, Sanjeev Kumar
  • Publication number: 20140089276
    Abstract: Systems and methods to accelerate compression and decompression with a search unit implemented in the processor core. According to an embodiment, a search unit may be implemented to perform compression or decompression on an input stream of data. The search unit may use a look-up table to identify appropriate compression or decompression symbols. The look-up table may be populated with a table derived using the variable length coding symbols of a sequence of vertices to be compressed or extracted from a received data stream to be decompressed. A comparator and a finite state machine may be implemented in the search unit to facilitate traversal of the look-up table.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Inventors: Nadathur Rajagopalan SATISH, Changkyu KIM, Jatin CHHUGANI
  • Publication number: 20140068226
    Abstract: In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.
    Type: Application
    Filed: March 12, 2013
    Publication date: March 6, 2014
    Inventors: MIKHAIL SMELYANSKIY, VICTOR LEE, CHRISTOPHER HUGHES, DAEHYUN KIM, YEN-KUANG CHEN, CHANGKYU KIM, JATIN CHHUGANI, ANTHONY D. NGUYEN, SANJEEV KUMAR
  • Publication number: 20130339395
    Abstract: Embodiments of techniques and systems for parallel processing of B+ trees are described. A parallel B+ tree processing module with partitioning and redistribution may include a set of threads executing a batch of B+ tree operations on a B+ tree in parallel. The batch of operations may be partitioned amongst the threads. Next, a search may be performed to determine which leaf nodes in the B+ tree are to be affected by which operations. Then, the threads may redistribute operations between each other such that multiple threads will not operate on the same leaf node. The threads may then perform B+ tree operations on the leaf nodes of the B+ tree in parallel. Subsequent modifications to nodes in the B+ may similarly be redistributed and performed in parallel as the threads work up the tree.
    Type: Application
    Filed: August 29, 2011
    Publication date: December 19, 2013
    Inventors: Jason D. Sewall, Changkyu Kim, Jatin Chhugani, Nadathur Rajagopalan Satish
  • Patent number: 8570336
    Abstract: A texture unit may be used utilized to perform general purpose mathematical computations such as dot products. This enables some general purpose computations and operations to be offloaded from a central processing unit to the texture unit. The texture unit may use linear interpolators in order to perform the dot product calculations.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: October 29, 2013
    Assignee: Intel Corporation
    Inventors: Victor W. Lee, Mikhail Smelyanskiy, Ganesh S. Dasika, Jose Gonzalez, Jatin Chhugani, Yen-Kuang Chen, Changkyu Kim, Julio Gago, Santiago Galan, Victor Moya Del Barrio
  • Patent number: 8564601
    Abstract: Parallel and vectored data structures may be used in a single instruction multiple data processor that applies the Gilbert-Johnson-Keerthi algorithm. As a result, the performance of multi-core processors doing graphics processing may be increased in some cases.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: October 22, 2013
    Assignee: Intel Corporation
    Inventors: Aleksey A. Bader, Mikhail Smelyanskiy, Jatin Chhugani
  • Patent number: 8533432
    Abstract: Methods, apparatuses and storage device associated with cache and/or socket sensitive breadth-first iterative traversal of a graph by parallel threads, are described. A vertices visited array (VIS) may be employed to track graph vertices visited. VIS may be partitioned into VIS sub-arrays, taking into consideration cache sizes of LLC, to reduce likelihood of evictions. Potential boundary vertices arrays (PBV) may be employed to store potential boundary vertices for a next iteration, for vertices being visited in a current iteration. The number of PBV generated for each thread may take into consideration a number of sockets, over which the processor cores employed are distributed. The threads may be load balanced; further data locality awareness to reduce inter-socket communication may be considered, and/or lock-and-atomic free update operations may be employed.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: September 10, 2013
    Assignee: Intel Corporation
    Inventors: Nadathur Rajagopalan Satish, Changkyu Kim, Jatin Chhugani, Jason D. Sewall
  • Patent number: 8463820
    Abstract: In some embodiments, the invention involves utilizing a tree merge sort in a platform to minimize cache reads/writes when sorting large amounts of data. An embodiment uses blocks of pre-sorted data residing in “leaf nodes” residing in memory storage. A pre-sorted block of data from each leaf node is read from memory and stored in faster cache memory. A tree merge sort is performed on the nodes that are cache resident until a block of data migrates to a root node. Sorted blocks reaching the root node are written to memory storage in an output list until all pre-sorted data blocks have been moved to cache and merged upward to the root. The completed output list in memory storage is a list of the fully sorted data. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: June 11, 2013
    Assignee: Intel Corporation
    Inventors: Jatin Chhugani, Sanjeev Kumar, Anthony-Trung D. Nguyen, Yen-Kuang Chen, Victor W. Lee, William Macy
  • Patent number: 8275805
    Abstract: A method of decreasing a total computation time for a visual simulation loop includes sharing a common data structure across each phase of the visual simulation loop by adapting the common data structure to a requirement for each particular phase prior to performing a computation for that particular phase.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: September 25, 2012
    Assignee: Intel Corporation
    Inventors: Jatin Chhugani, Bryan Catanzaro, Sanjeev Kumar, Changkyu Kim, Nadathur Rajagopalan Satish
  • Publication number: 20120137074
    Abstract: A method and system to perform stream buffer management instructions in a processor. The stream buffer management instructions facilitate the creation and usage of a dedicated memory space or stream buffer of the processor in one embodiment of the invention. The dedicated memory space is a contiguous memory space and has a sequential or linear addressing scheme in one embodiment of the invention. The processor has logic to execute a stream buffer management instruction to copy data from a source memory address to a destination memory address that is specified with a desired level of memory hierarchy.
    Type: Application
    Filed: November 29, 2010
    Publication date: May 31, 2012
    Inventors: Daehyun Kim, Changkyu Kim, Victor W. Lee, Jatin Chhugani, Nadathur Rajagopalan Satish
  • Publication number: 20110238680
    Abstract: A method of decreasing a total computation time for a visual simulation loop includes sharing a common data structure across each phase of the visual simulation loop by adapting the common data structure to a requirement for each particular phase prior to performing a computation for that particular phase.
    Type: Application
    Filed: March 26, 2010
    Publication date: September 29, 2011
    Inventors: Jatin Chhugani, Bryan Catanzaro, Sanjeev Kumar, Changkyu Kim, Nadathur Rajagopalan Satish
  • Publication number: 20110161060
    Abstract: A method of computing a collision-free velocity (117, 217) for an agent (110) in a crowd simulation environment (100) comprises identifying a quadratic optimization problem that corresponds to the collision-free velocity, and finding an exact solution for the quadratic optimization problem by using a geometric approach.
    Type: Application
    Filed: December 29, 2009
    Publication date: June 30, 2011
    Inventors: Changkyu Kim, Stephen J. Guy, Anthony-Trung D. Nguyen, Daehyun Kim, Jatin Chhugani
  • Publication number: 20110148896
    Abstract: A region or group of pixels may be textured as a unit, using a range specifier and one or more anchor pixels to define the group. In some embodiments, processing grouped pixels improves efficiency.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Inventors: Victor W. Lee, Ganesh S. Dasika, Mikhail Smelyanskiy, Jose Gonzalez, Changkyu Kim, Jatin Chhugani, Yen-Kuang Chen, Julio Gago, Santiago Galan, Victor Moya Del Barrio
  • Publication number: 20110153996
    Abstract: Parallel and vectored data structures may be used in a single instruction multiple data processor that applies the Gilbert-Johnson-Keerthi algorithm. As a result, the performance of multi-core processors doing graphics processing may be increased in some cases.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Inventors: Aleksey A. Bader, Mikhail Smelyanskiy, Jatin Chhugani