Patents by Inventor Jatin Fultaria

Jatin Fultaria has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for testing of a memory with redundancy elements
    Patent number: 8458545
    Abstract: A circuit includes an input node configured to receive a test address input signal and circuitry configured to generate, from a first part of the test address input signal, a first address signal that selects a first address of a first part of a circuit to be tested and further generate, from a second part of the test address input signal, a second signal configured to select a second part of the circuit to be tested. Test circuitry is then configured to use the first address and the second part in a test mode.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: June 4, 2013
    Assignee: STMicroelectronics International N.V.
    Inventors: Tanmoy Roy, Harsh Rawat, Swapnil Bahl, Amit Chhabra, Nitin Jain, Jatin Fultaria
  • METHOD AND APPARATUS FOR TESTING OF A MEMORY WITH REDUNDANCY ELEMENTS
    Publication number: 20120137188
    Abstract: A circuit includes an input node configured to receive a test address input signal and circuitry configured to generate, from a first part of the test address input signal, a first address signal that selects a first address of a first part of a circuit to be tested and further generate, from a second part of the test address input signal, a second signal configured to select a second part of the circuit to be tested. Test circuitry is then configured to use the first address and the second part in a test mode.
    Type: Application
    Filed: November 29, 2010
    Publication date: May 31, 2012
    Applicant: STMICROELECTRONICS PVT. LTD.
    Inventors: Tanmoy Roy, Harsh Rawat, Swapnil Bahl, Amit Chhabra, Nitin Jain, Jatin Fultaria