Patents by Inventor Jatin Verma

Jatin Verma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11860751
    Abstract: Test packets may be received at a design under test (DUT) from an automated test equipment (ATE) over a serializer/deserializer (SERDES) connection between the ATE and the DUT. The test packets may include test pattern data to test the DUT. The test pattern data may be applied to the DUT using a set of scan chains and test response data corresponding to the test pattern data may be obtained. The test response data may be received by a circuit in the DUT at irregular time intervals. Response packets may be sent to the ATE by the circuit in the DUT at regular time intervals, where the response packets may include a portion of the test response data (which may be encoded using an encoding technique), and where the response packets may be sent to ATE over the SERDES connection.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: January 2, 2024
    Assignee: Synopsys, Inc.
    Inventors: Abhijeet Samudra, Ajay Nagarandal, Anubhav Sinha, Luis M. Cruz, Milin Kaushik Raijada, Ramalingam Kolisetti, Naresh Thakur, Saransh Nagaich, Jatin Verma