Abstract: An optical method for measuring a trench depth, applicable to a substrate having a trench therein, wherein the substrate has a first surface, and the trench has a bottom surface to serve as a second surface as well as a depth. The method involves measuring a total reflectance from the substrate using different wavelengths, wherein the total reflectance is determined by a first actual reflectance from the first surface, a second actual reflectance from the second surface, and a scattering factor. The second actual reflectance is then determined from the measurement of the first actual reflectance from the first surface and the calculation result of the scattering factor. Since a trench depth is determined from the second actual reflectance, the trench depth is calculated after acquiring the second actual reflectance.

Abstract: A method for fabricating very narrow contacts on semiconductor substrate for increasing the packing density of devices on Ultra Large Scale Integration (ULSI) circuits was achieved. The method involves using conventional photolithographic techniques and anisotropic plasma etching to etch openings in a conducting layer and partially etch into an underlying planar insulating layer that covers and isolates the devices and device contact areas. Another conformal conducting layer is deposited on the substrate and in the openings and then etched back to form sidewall spacers in the openings. Using the original conducting layer and the sidewall spacers as an etch mask, the planar insulating layer is anisotropically etched within the sidewall spacers to form very narrow (small) contact opening to the desired device contact areas.

Abstract: A method for fabricating MOSFET devices, with narrow gate structures, and narrow spaces between gate structures, has been developed. The addition of a rough surfaced silicon layer, as part of the gate structure, minimizes the amount of reflective and scattered light, resulting during the gate photolithographic processing. The reduction in reflective and scattered greatly enhances the ability to achieve sub-micron lines and spaces. The rough surfaced silicon can remain as a part of the gate structure, and is obtained by chemical vapor deposition of either an amorphous silicon, or a hemi-spherical grained silicon film.